212 lines
6.0 KiB
C
212 lines
6.0 KiB
C
/*
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* arch/arm/mach-orion5x/irq.c
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*
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* Core IRQ functions for Marvell Orion System On Chip
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*
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* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/orion5x.h>
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#include <asm/plat-orion/irq.h>
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#include "common.h"
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/*****************************************************************************
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* Orion GPIO IRQ
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*
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* GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
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* value of the line or the opposite value.
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*
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* Level IRQ handlers: DATA_IN is used directly as cause register.
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* Interrupt are masked by LEVEL_MASK registers.
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
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* Interrupt are masked by EDGE_MASK registers.
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps
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* the polarity to catch the next line transaction.
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* This is a race condition that might not perfectly
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* work on some use cases.
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*
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* Every eight GPIO lines are grouped (OR'ed) before going up to main
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* cause register.
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*
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* EDGE cause mask
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* data-in /--------| |-----| |----\
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* -----| |----- ---- to main cause reg
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* X \----------------| |----/
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* polarity LEVEL mask
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*
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****************************************************************************/
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static void orion5x_gpio_irq_ack(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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if (irq_desc[irq].status & IRQ_LEVEL)
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/*
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* Mask bit for level interrupt
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*/
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orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
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else
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/*
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* Clear casue bit for egde interrupt
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*/
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orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
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}
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static void orion5x_gpio_irq_mask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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if (irq_desc[irq].status & IRQ_LEVEL)
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orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
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else
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orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
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}
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static void orion5x_gpio_irq_unmask(u32 irq)
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{
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int pin = irq_to_gpio(irq);
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if (irq_desc[irq].status & IRQ_LEVEL)
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orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
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else
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orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
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}
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static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
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{
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int pin = irq_to_gpio(irq);
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struct irq_desc *desc;
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if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
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printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
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"(irq %d, pin %d).\n", irq, pin);
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return -EINVAL;
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}
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desc = irq_desc + irq;
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switch (type) {
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case IRQT_HIGH:
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desc->handle_irq = handle_level_irq;
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desc->status |= IRQ_LEVEL;
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orion5x_clrbits(GPIO_IN_POL, (1 << pin));
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break;
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case IRQT_LOW:
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desc->handle_irq = handle_level_irq;
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desc->status |= IRQ_LEVEL;
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orion5x_setbits(GPIO_IN_POL, (1 << pin));
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break;
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case IRQT_RISING:
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desc->handle_irq = handle_edge_irq;
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desc->status &= ~IRQ_LEVEL;
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orion5x_clrbits(GPIO_IN_POL, (1 << pin));
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break;
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case IRQT_FALLING:
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desc->handle_irq = handle_edge_irq;
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desc->status &= ~IRQ_LEVEL;
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orion5x_setbits(GPIO_IN_POL, (1 << pin));
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break;
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case IRQT_BOTHEDGE:
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desc->handle_irq = handle_edge_irq;
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desc->status &= ~IRQ_LEVEL;
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/*
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* set initial polarity based on current input level
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*/
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if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN))
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& (1 << pin))
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orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
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else
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orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
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break;
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default:
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printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
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return -EINVAL;
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}
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desc->status &= ~IRQ_TYPE_SENSE_MASK;
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desc->status |= type & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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static struct irq_chip orion5x_gpio_irq_chip = {
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.name = "Orion-IRQ-GPIO",
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.ack = orion5x_gpio_irq_ack,
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.mask = orion5x_gpio_irq_mask,
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.unmask = orion5x_gpio_irq_unmask,
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.set_type = orion5x_gpio_set_irq_type,
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};
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static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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u32 cause, offs, pin;
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BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
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offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
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cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) |
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(orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK));
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for (pin = offs; pin < offs + 8; pin++) {
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if (cause & (1 << pin)) {
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irq = gpio_to_irq(pin);
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desc = irq_desc + irq;
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if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
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/* Swap polarity (race with GPIO line) */
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u32 polarity = orion5x_read(GPIO_IN_POL);
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polarity ^= 1 << pin;
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orion5x_write(GPIO_IN_POL, polarity);
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}
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desc_handle_irq(irq, desc);
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}
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}
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}
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static void __init orion5x_init_gpio_irq(void)
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{
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int i;
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struct irq_desc *desc;
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/*
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* Mask and clear GPIO IRQ interrupts
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*/
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orion5x_write(GPIO_LEVEL_MASK, 0x0);
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orion5x_write(GPIO_EDGE_MASK, 0x0);
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orion5x_write(GPIO_EDGE_CAUSE, 0x0);
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/*
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* Register chained level handlers for GPIO IRQs by default.
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* User can use set_type() if he wants to use edge types handlers.
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*/
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for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
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set_irq_chip(i, &orion5x_gpio_irq_chip);
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set_irq_handler(i, handle_level_irq);
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desc = irq_desc + i;
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desc->status |= IRQ_LEVEL;
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set_irq_flags(i, IRQF_VALID);
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}
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set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
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set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
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set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
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set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
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}
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/*****************************************************************************
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* Orion Main IRQ
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****************************************************************************/
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static void __init orion5x_init_main_irq(void)
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{
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orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
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}
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void __init orion5x_init_irq(void)
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{
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orion5x_init_main_irq();
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orion5x_init_gpio_irq();
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}
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