338 lines
8.6 KiB
C
338 lines
8.6 KiB
C
/*
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* arch/ppc/platforms/4xx/ebony.c
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*
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* Ebony board specific routines
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*
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003-2005 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/types.h>
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#include <linux/major.h>
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#include <linux/blkdev.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/ide.h>
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#include <linux/initrd.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/tty.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/ocp.h>
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#include <asm/pci-bridge.h>
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#include <asm/time.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/ppcboot.h>
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#include <asm/tlbflush.h>
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#include <syslib/gen550.h>
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#include <syslib/ibm440gp_common.h>
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extern bd_t __res;
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static struct ibm44x_clocks clocks __initdata;
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/*
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* Ebony external IRQ triggering/polarity settings
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*/
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unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: PCI slot 0 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ1: PCI slot 1 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 2 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 3 */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ4: IRDA */
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(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE), /* IRQ5: SMI pushbutton */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ6: PHYs */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ7: AUX */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ10: EXT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ11: EXT */
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ12: EXT */
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};
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static void __init
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ebony_calibrate_decr(void)
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{
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unsigned int freq;
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/*
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* Determine system clock speed
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*
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* If we are on Rev. B silicon, then use
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* default external system clock. If we are
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* on Rev. C silicon then errata forces us to
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* use the internal clock.
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*/
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if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
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freq = EBONY_440GP_RB_SYSCLK;
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else
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freq = EBONY_440GP_RC_SYSCLK;
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ibm44x_calibrate_decr(freq);
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}
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static int
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ebony_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "vendor\t\t: IBM\n");
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seq_printf(m, "machine\t\t: Ebony\n");
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return 0;
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}
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static inline int
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ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 23, 23, 23, 23 }, /* IDSEL 1 - PCI Slot 0 */
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{ 24, 24, 24, 24 }, /* IDSEL 2 - PCI Slot 1 */
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{ 25, 25, 25, 25 }, /* IDSEL 3 - PCI Slot 2 */
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{ 26, 26, 26, 26 }, /* IDSEL 4 - PCI Slot 3 */
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};
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const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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#define PCIX_WRITEL(value, offset) \
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(writel(value, pcix_reg_base + offset))
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/*
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* FIXME: This is only here to "make it work". This will move
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* to a ibm_pcix.c which will contain a generic IBM PCIX bridge
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* configuration library. -Matt
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*/
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static void __init
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ebony_setup_pcix(void)
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{
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void __iomem *pcix_reg_base;
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pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
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/* Disable all windows */
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PCIX_WRITEL(0, PCIX0_POM0SA);
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PCIX_WRITEL(0, PCIX0_POM1SA);
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PCIX_WRITEL(0, PCIX0_POM2SA);
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PCIX_WRITEL(0, PCIX0_PIM0SA);
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PCIX_WRITEL(0, PCIX0_PIM1SA);
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PCIX_WRITEL(0, PCIX0_PIM2SA);
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/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
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PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
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PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
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PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
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PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
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PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
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/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
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PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
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PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
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PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
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eieio();
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}
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static void __init
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ebony_setup_hose(void)
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{
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struct pci_controller *hose;
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/* Configure windows on the PCI-X host bridge */
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ebony_setup_pcix();
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hose = pcibios_alloc_controller();
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if (!hose)
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return;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
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pci_init_resource(&hose->io_resource,
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EBONY_PCI_LOWER_IO,
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EBONY_PCI_UPPER_IO,
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IORESOURCE_IO,
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"PCI host bridge");
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pci_init_resource(&hose->mem_resources[0],
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EBONY_PCI_LOWER_MEM,
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EBONY_PCI_UPPER_MEM,
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IORESOURCE_MEM,
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"PCI host bridge");
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hose->io_space.start = EBONY_PCI_LOWER_IO;
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hose->io_space.end = EBONY_PCI_UPPER_IO;
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hose->mem_space.start = EBONY_PCI_LOWER_MEM;
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hose->mem_space.end = EBONY_PCI_UPPER_MEM;
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hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
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isa_io_base = (unsigned long)hose->io_base_virt;
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setup_indirect_pci(hose,
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EBONY_PCI_CFGA_PLB32,
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EBONY_PCI_CFGD_PLB32);
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hose->set_cfg_type = 1;
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hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
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ppc_md.pci_swizzle = common_swizzle;
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ppc_md.pci_map_irq = ebony_map_irq;
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}
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TODC_ALLOC();
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static void __init
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ebony_early_serial_map(void)
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{
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struct uart_port port;
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/* Setup ioremapped serial port access */
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memset(&port, 0, sizeof(port));
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port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
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port.irq = 0;
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port.uartclk = clocks.uart0;
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port.regshift = 0;
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port.iotype = SERIAL_IO_MEM;
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port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
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port.line = 0;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 0 failed\n");
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Configure debug serial access */
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gen550_init(0, &port);
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/* Purge TLB entry added in head_44x.S for early serial access */
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_tlbie(UART0_IO_BASE);
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#endif
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port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
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port.irq = 1;
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port.uartclk = clocks.uart1;
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port.line = 1;
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if (early_serial_setup(&port) != 0) {
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printk("Early serial init of port 1 failed\n");
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
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/* Configure debug serial access */
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gen550_init(1, &port);
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#endif
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}
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static void __init
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ebony_setup_arch(void)
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{
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struct ocp_def *def;
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struct ocp_func_emac_data *emacdata;
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/* Set mac_addr for each EMAC */
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def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
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emacdata = def->additions;
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emacdata->phy_map = 0x00000001; /* Skip 0x00 */
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emacdata->phy_mode = PHY_MODE_RMII;
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memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
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def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
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emacdata = def->additions;
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emacdata->phy_map = 0x00000001; /* Skip 0x00 */
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emacdata->phy_mode = PHY_MODE_RMII;
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memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
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/*
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* Determine various clocks.
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* To be completely correct we should get SysClk
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* from FPGA, because it can be changed by on-board switches
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* --ebs
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*/
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ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
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ocp_sys_info.opb_bus_freq = clocks.opb;
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/* Setup TODC access */
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TODC_INIT(TODC_TYPE_DS1743,
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0,
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0,
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ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
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8);
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/* init to some ~sane value until calibrate_delay() runs */
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loops_per_jiffy = 50000000/HZ;
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/* Setup PCI host bridge */
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ebony_setup_hose();
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_HDA1;
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#endif
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ebony_early_serial_map();
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/* Identify the system */
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printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
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}
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void __init platform_init(unsigned long r3, unsigned long r4,
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unsigned long r5, unsigned long r6, unsigned long r7)
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{
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ibm44x_platform_init(r3, r4, r5, r6, r7);
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ppc_md.setup_arch = ebony_setup_arch;
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ppc_md.show_cpuinfo = ebony_show_cpuinfo;
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ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */
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ppc_md.calibrate_decr = ebony_calibrate_decr;
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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#ifdef CONFIG_KGDB
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ppc_md.early_serial_map = ebony_early_serial_map;
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#endif
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}
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