64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/*
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* PPC440SPe definitions
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*
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* Roland Dreier <rolandd@cisco.com>
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* Copyright (c) 2005 Cisco Systems. All rights reserved.
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*
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2004-2005 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef __PPC_PLATFORMS_PPC440SPE_H
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#define __PPC_PLATFORMS_PPC440SPE_H
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#include <asm/ibm44x.h>
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/* UART */
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#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL
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#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL
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#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL
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#define UART0_INT 0
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#define UART1_INT 1
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#define UART2_INT 37
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/* Clock and Power Management */
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#define IBM_CPM_IIC0 0x80000000 /* IIC interface */
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#define IBM_CPM_IIC1 0x40000000 /* IIC interface */
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#define IBM_CPM_PCI 0x20000000 /* PCI bridge */
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#define IBM_CPM_CPU 0x02000000 /* processor core */
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#define IBM_CPM_DMA 0x01000000 /* DMA controller */
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#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */
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#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */
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#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */
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#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */
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#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */
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#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */
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#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */
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#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */
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#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */
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#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */
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#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */
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#define IBM_CPM_UART0 0x00000200 /* serial port 0 */
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#define IBM_CPM_UART1 0x00000100 /* serial port 1 */
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#define IBM_CPM_UART2 0x00000100 /* serial port 1 */
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#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */
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#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */
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#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */
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#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
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| IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
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| IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
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| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
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| IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
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| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
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| IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
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#endif /* __PPC_PLATFORMS_PPC440SP_H */
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#endif /* __KERNEL__ */
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