274 lines
6.1 KiB
C
274 lines
6.1 KiB
C
/*
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* linux/arch/arm/mach-pxa/irq.c
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*
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* Generic PXA IRQ handling
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/bitops.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/exception.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#include "generic.h"
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#define ICIP (0x000)
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#define ICMR (0x004)
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#define ICLR (0x008)
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#define ICFR (0x00c)
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#define ICPR (0x010)
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#define ICCR (0x014)
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#define ICHP (0x018)
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#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
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((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
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(0x144 + (((i) - 64) << 2)))
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#define ICHP_VAL_IRQ (1 << 31)
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#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
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#define IPR_VALID (1 << 31)
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#define MAX_INTERNAL_IRQS 128
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/*
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* This is for peripheral IRQs internal to the PXA chip.
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*/
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static void __iomem *pxa_irq_base;
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static int pxa_internal_irq_nr;
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static bool cpu_has_ipr;
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static struct irq_domain *pxa_irq_domain;
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static inline void __iomem *irq_base(int i)
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{
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static unsigned long phys_base_offset[] = {
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0x0,
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0x9c,
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0x130,
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};
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return pxa_irq_base + phys_base_offset[i];
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}
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void pxa_mask_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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irq_hw_number_t irq = irqd_to_hwirq(d);
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uint32_t icmr = __raw_readl(base + ICMR);
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icmr &= ~BIT(irq & 0x1f);
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__raw_writel(icmr, base + ICMR);
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}
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void pxa_unmask_irq(struct irq_data *d)
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{
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void __iomem *base = irq_data_get_irq_chip_data(d);
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irq_hw_number_t irq = irqd_to_hwirq(d);
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uint32_t icmr = __raw_readl(base + ICMR);
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icmr |= BIT(irq & 0x1f);
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__raw_writel(icmr, base + ICMR);
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}
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static struct irq_chip pxa_internal_irq_chip = {
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.name = "SC",
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.irq_ack = pxa_mask_irq,
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.irq_mask = pxa_mask_irq,
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.irq_unmask = pxa_unmask_irq,
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};
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asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
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{
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uint32_t icip, icmr, mask;
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do {
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icip = __raw_readl(pxa_irq_base + ICIP);
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icmr = __raw_readl(pxa_irq_base + ICMR);
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mask = icip & icmr;
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if (mask == 0)
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break;
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handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
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} while (1);
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}
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asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
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{
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uint32_t ichp;
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do {
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__asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
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if ((ichp & ICHP_VAL_IRQ) == 0)
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break;
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handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
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} while (1);
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}
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static int pxa_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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void __iomem *base = irq_base(hw / 32);
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/* initialize interrupt priority */
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if (cpu_has_ipr)
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__raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw));
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irq_set_chip_and_handler(virq, &pxa_internal_irq_chip,
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handle_level_irq);
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irq_set_chip_data(virq, base);
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return 0;
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}
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static const struct irq_domain_ops pxa_irq_ops = {
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.map = pxa_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static __init void
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pxa_init_irq_common(struct device_node *node, int irq_nr,
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int (*fn)(struct irq_data *, unsigned int))
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{
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int n;
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pxa_internal_irq_nr = irq_nr;
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pxa_irq_domain = irq_domain_add_legacy(node, irq_nr,
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PXA_IRQ(0), 0,
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&pxa_irq_ops, NULL);
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if (!pxa_irq_domain)
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panic("Unable to add PXA IRQ domain\n");
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irq_set_default_host(pxa_irq_domain);
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for (n = 0; n < irq_nr; n += 32) {
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void __iomem *base = irq_base(n >> 5);
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__raw_writel(0, base + ICMR); /* disable all IRQs */
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__raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */
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}
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/* only unmasked interrupts kick us out of idle */
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__raw_writel(1, irq_base(0) + ICCR);
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pxa_internal_irq_chip.irq_set_wake = fn;
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}
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void __init pxa_init_irq(int irq_nr, int (*fn)(struct irq_data *, unsigned int))
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{
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BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
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pxa_irq_base = io_p2v(0x40d00000);
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cpu_has_ipr = !cpu_is_pxa25x();
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pxa_init_irq_common(NULL, irq_nr, fn);
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}
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#ifdef CONFIG_PM
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static unsigned long saved_icmr[MAX_INTERNAL_IRQS/32];
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static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
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static int pxa_irq_suspend(void)
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{
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int i;
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for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
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void __iomem *base = irq_base(i);
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saved_icmr[i] = __raw_readl(base + ICMR);
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__raw_writel(0, base + ICMR);
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}
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if (cpu_has_ipr) {
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for (i = 0; i < pxa_internal_irq_nr; i++)
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saved_ipr[i] = __raw_readl(pxa_irq_base + IPR(i));
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}
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return 0;
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}
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static void pxa_irq_resume(void)
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{
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int i;
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for (i = 0; i < pxa_internal_irq_nr / 32; i++) {
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void __iomem *base = irq_base(i);
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__raw_writel(saved_icmr[i], base + ICMR);
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__raw_writel(0, base + ICLR);
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}
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if (cpu_has_ipr)
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for (i = 0; i < pxa_internal_irq_nr; i++)
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__raw_writel(saved_ipr[i], pxa_irq_base + IPR(i));
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__raw_writel(1, pxa_irq_base + ICCR);
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}
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#else
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#define pxa_irq_suspend NULL
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#define pxa_irq_resume NULL
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#endif
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struct syscore_ops pxa_irq_syscore_ops = {
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.suspend = pxa_irq_suspend,
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.resume = pxa_irq_resume,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id intc_ids[] __initconst = {
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{ .compatible = "marvell,pxa-intc", },
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{}
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};
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void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int))
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{
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struct device_node *node;
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struct resource res;
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int ret;
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node = of_find_matching_node(NULL, intc_ids);
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if (!node) {
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pr_err("Failed to find interrupt controller in arch-pxa\n");
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return;
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}
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ret = of_property_read_u32(node, "marvell,intc-nr-irqs",
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&pxa_internal_irq_nr);
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if (ret) {
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pr_err("Not found marvell,intc-nr-irqs property\n");
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return;
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}
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ret = of_address_to_resource(node, 0, &res);
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if (ret < 0) {
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pr_err("No registers defined for node\n");
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return;
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}
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pxa_irq_base = io_p2v(res.start);
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if (of_find_property(node, "marvell,intc-priority", NULL))
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cpu_has_ipr = 1;
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ret = irq_alloc_descs(-1, 0, pxa_internal_irq_nr, 0);
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if (ret < 0) {
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pr_err("Failed to allocate IRQ numbers\n");
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return;
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}
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pxa_init_irq_common(node, pxa_internal_irq_nr, fn);
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}
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#endif /* CONFIG_OF */
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