364 lines
9.3 KiB
C
364 lines
9.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
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*
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* Routines for PCI DMA mapping. See Documentation/DMA-API.txt for
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* a description of how these routines should be used.
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*/
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#include <linux/module.h>
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#include <asm/dma.h>
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#include <asm/sn/sn_sal.h>
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#include "pci/pcibus_provider_defs.h"
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#include "pci/pcidev.h"
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#include "pci/pcibr_provider.h"
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#define SG_ENT_VIRT_ADDRESS(sg) (page_address((sg)->page) + (sg)->offset)
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#define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
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/**
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* sn_dma_supported - test a DMA mask
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* @dev: device to test
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* @mask: DMA mask to test
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*
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* Return whether the given PCI device DMA address mask can be supported
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* properly. For example, if your device can only drive the low 24-bits
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* during PCI bus mastering, then you would pass 0x00ffffff as the mask to
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* this function. Of course, SN only supports devices that have 32 or more
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* address bits when using the PMU.
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*/
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int sn_dma_supported(struct device *dev, u64 mask)
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{
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BUG_ON(dev->bus != &pci_bus_type);
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if (mask < 0x7fffffff)
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return 0;
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return 1;
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}
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EXPORT_SYMBOL(sn_dma_supported);
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/**
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* sn_dma_set_mask - set the DMA mask
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* @dev: device to set
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* @dma_mask: new mask
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*
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* Set @dev's DMA mask if the hw supports it.
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*/
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int sn_dma_set_mask(struct device *dev, u64 dma_mask)
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{
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BUG_ON(dev->bus != &pci_bus_type);
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if (!sn_dma_supported(dev, dma_mask))
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return 0;
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*dev->dma_mask = dma_mask;
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return 1;
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}
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EXPORT_SYMBOL(sn_dma_set_mask);
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/**
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* sn_dma_alloc_coherent - allocate memory for coherent DMA
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* @dev: device to allocate for
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* @size: size of the region
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* @dma_handle: DMA (bus) address
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* @flags: memory allocation flags
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*
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* dma_alloc_coherent() returns a pointer to a memory region suitable for
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* coherent DMA traffic to/from a PCI device. On SN platforms, this means
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* that @dma_handle will have the %PCIIO_DMA_CMD flag set.
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*
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* This interface is usually used for "command" streams (e.g. the command
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* queue for a SCSI controller). See Documentation/DMA-API.txt for
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* more information.
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*/
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void *sn_dma_alloc_coherent(struct device *dev, size_t size,
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dma_addr_t * dma_handle, int flags)
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{
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void *cpuaddr;
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unsigned long phys_addr;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(to_pci_dev(dev));
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BUG_ON(dev->bus != &pci_bus_type);
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/*
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* Allocate the memory.
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* FIXME: We should be doing alloc_pages_node for the node closest
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* to the PCI device.
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*/
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if (!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size))))
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return NULL;
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memset(cpuaddr, 0x0, size);
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/* physical addr. of the memory we just got */
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phys_addr = __pa(cpuaddr);
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/*
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* 64 bit address translations should never fail.
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* 32 bit translations can fail if there are insufficient mapping
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* resources.
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*/
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*dma_handle = pcibr_dma_map(pcidev_info, phys_addr, size,
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SN_PCIDMA_CONSISTENT);
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if (!*dma_handle) {
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printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
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free_pages((unsigned long)cpuaddr, get_order(size));
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return NULL;
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}
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return cpuaddr;
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}
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EXPORT_SYMBOL(sn_dma_alloc_coherent);
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/**
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* sn_pci_free_coherent - free memory associated with coherent DMAable region
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* @dev: device to free for
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* @size: size to free
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* @cpu_addr: kernel virtual address to free
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* @dma_handle: DMA address associated with this region
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*
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* Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
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* any associated IOMMU mappings.
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*/
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void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
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dma_addr_t dma_handle)
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{
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(to_pci_dev(dev));
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BUG_ON(dev->bus != &pci_bus_type);
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pcibr_dma_unmap(pcidev_info, dma_handle, 0);
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free_pages((unsigned long)cpu_addr, get_order(size));
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}
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EXPORT_SYMBOL(sn_dma_free_coherent);
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/**
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* sn_dma_map_single - map a single page for DMA
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* @dev: device to map for
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* @cpu_addr: kernel virtual address of the region to map
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* @size: size of the region
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* @direction: DMA direction
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*
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* Map the region pointed to by @cpu_addr for DMA and return the
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* DMA address.
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*
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* We map this to the one step pcibr_dmamap_trans interface rather than
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* the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
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* no way of saving the dmamap handle from the alloc to later free
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* (which is pretty much unacceptable).
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*
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* TODO: simplify our interface;
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* figure out how to save dmamap handle so can use two step.
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*/
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dma_addr_t sn_dma_map_single(struct device *dev, void *cpu_addr, size_t size,
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int direction)
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{
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dma_addr_t dma_addr;
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unsigned long phys_addr;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(to_pci_dev(dev));
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BUG_ON(dev->bus != &pci_bus_type);
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phys_addr = __pa(cpu_addr);
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dma_addr = pcibr_dma_map(pcidev_info, phys_addr, size, 0);
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if (!dma_addr) {
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printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
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return 0;
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}
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return dma_addr;
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}
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EXPORT_SYMBOL(sn_dma_map_single);
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/**
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* sn_dma_unmap_single - unamp a DMA mapped page
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* @dev: device to sync
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* @dma_addr: DMA address to sync
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* @size: size of region
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* @direction: DMA direction
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*
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* This routine is supposed to sync the DMA region specified
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* by @dma_handle into the coherence domain. On SN, we're always cache
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* coherent, so we just need to free any ATEs associated with this mapping.
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*/
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void sn_dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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int direction)
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{
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(to_pci_dev(dev));
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BUG_ON(dev->bus != &pci_bus_type);
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pcibr_dma_unmap(pcidev_info, dma_addr, direction);
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}
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EXPORT_SYMBOL(sn_dma_unmap_single);
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/**
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* sn_dma_unmap_sg - unmap a DMA scatterlist
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* @dev: device to unmap
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* @sg: scatterlist to unmap
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* @nhwentries: number of scatterlist entries
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* @direction: DMA direction
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*
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* Unmap a set of streaming mode DMA translations.
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*/
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void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sg,
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int nhwentries, int direction)
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{
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int i;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(to_pci_dev(dev));
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BUG_ON(dev->bus != &pci_bus_type);
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for (i = 0; i < nhwentries; i++, sg++) {
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pcibr_dma_unmap(pcidev_info, sg->dma_address, direction);
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sg->dma_address = (dma_addr_t) NULL;
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sg->dma_length = 0;
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}
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}
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EXPORT_SYMBOL(sn_dma_unmap_sg);
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/**
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* sn_dma_map_sg - map a scatterlist for DMA
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* @dev: device to map for
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* @sg: scatterlist to map
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* @nhwentries: number of entries
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* @direction: direction of the DMA transaction
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*
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* Maps each entry of @sg for DMA.
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*/
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int sn_dma_map_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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int direction)
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{
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unsigned long phys_addr;
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struct scatterlist *saved_sg = sg;
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struct pcidev_info *pcidev_info = SN_PCIDEV_INFO(to_pci_dev(dev));
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int i;
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BUG_ON(dev->bus != &pci_bus_type);
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/*
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* Setup a DMA address for each entry in the scatterlist.
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*/
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for (i = 0; i < nhwentries; i++, sg++) {
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phys_addr = SG_ENT_PHYS_ADDRESS(sg);
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sg->dma_address = pcibr_dma_map(pcidev_info, phys_addr,
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sg->length, 0);
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if (!sg->dma_address) {
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printk(KERN_ERR "%s: out of ATEs\n", __FUNCTION__);
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/*
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* Free any successfully allocated entries.
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*/
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if (i > 0)
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sn_dma_unmap_sg(dev, saved_sg, i, direction);
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return 0;
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}
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sg->dma_length = sg->length;
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}
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return nhwentries;
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}
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EXPORT_SYMBOL(sn_dma_map_sg);
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void sn_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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size_t size, int direction)
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{
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BUG_ON(dev->bus != &pci_bus_type);
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}
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EXPORT_SYMBOL(sn_dma_sync_single_for_cpu);
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void sn_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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size_t size, int direction)
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{
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BUG_ON(dev->bus != &pci_bus_type);
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}
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EXPORT_SYMBOL(sn_dma_sync_single_for_device);
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void sn_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
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int nelems, int direction)
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{
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BUG_ON(dev->bus != &pci_bus_type);
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}
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EXPORT_SYMBOL(sn_dma_sync_sg_for_cpu);
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void sn_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
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int nelems, int direction)
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{
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BUG_ON(dev->bus != &pci_bus_type);
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}
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EXPORT_SYMBOL(sn_dma_sync_sg_for_device);
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int sn_dma_mapping_error(dma_addr_t dma_addr)
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{
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return 0;
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}
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EXPORT_SYMBOL(sn_dma_mapping_error);
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char *sn_pci_get_legacy_mem(struct pci_bus *bus)
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{
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if (!SN_PCIBUS_BUSSOFT(bus))
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return ERR_PTR(-ENODEV);
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return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
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}
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int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
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{
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unsigned long addr;
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int ret;
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if (!SN_PCIBUS_BUSSOFT(bus))
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return -ENODEV;
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addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
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addr += port;
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ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
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if (ret == 2)
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return -EINVAL;
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if (ret == 1)
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*val = -1;
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return size;
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}
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int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
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{
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int ret = size;
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unsigned long paddr;
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unsigned long *addr;
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if (!SN_PCIBUS_BUSSOFT(bus)) {
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ret = -ENODEV;
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goto out;
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}
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/* Put the phys addr in uncached space */
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paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
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paddr += port;
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addr = (unsigned long *)paddr;
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switch (size) {
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case 1:
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*(volatile u8 *)(addr) = (u8)(val);
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break;
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case 2:
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*(volatile u16 *)(addr) = (u16)(val);
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break;
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case 4:
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*(volatile u32 *)(addr) = (u32)(val);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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out:
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return ret;
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}
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