301 lines
8.2 KiB
C
301 lines
8.2 KiB
C
/*
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* Copyright 2013 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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/* Machine-generated file; do not edit. */
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#ifndef __ARCH_UART_H__
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#define __ARCH_UART_H__
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#include <arch/abi.h>
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#include <arch/uart_def.h>
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#ifndef __ASSEMBLER__
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/* Divisor. */
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__extension__
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typedef union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/*
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* Baud Rate Divisor. Desired_baud_rate = REF_CLK frequency / (baud *
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* 16).
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* Note: REF_CLK is always 125 MHz, the default
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* divisor = 68, baud rate = 125M/(68*16) = 115200 baud.
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*/
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uint_reg_t divisor : 12;
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/* Reserved. */
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uint_reg_t __reserved : 52;
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#else /* __BIG_ENDIAN__ */
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uint_reg_t __reserved : 52;
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uint_reg_t divisor : 12;
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#endif
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};
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uint_reg_t word;
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} UART_DIVISOR_t;
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/* FIFO Count. */
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__extension__
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typedef union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/*
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* n: n active entries in the receive FIFO (max is 2**8). Each entry has
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* 8 bits.
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* 0: no active entry in the receive FIFO (that is empty).
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*/
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uint_reg_t rfifo_count : 9;
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/* Reserved. */
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uint_reg_t __reserved_0 : 7;
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/*
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* n: n active entries in the transmit FIFO (max is 2**8). Each entry has
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* 8 bits.
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* 0: no active entry in the transmit FIFO (that is empty).
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*/
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uint_reg_t tfifo_count : 9;
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/* Reserved. */
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uint_reg_t __reserved_1 : 7;
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/*
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* n: n active entries in the write FIFO (max is 2**2). Each entry has 8
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* bits.
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* 0: no active entry in the write FIFO (that is empty).
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*/
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uint_reg_t wfifo_count : 3;
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/* Reserved. */
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uint_reg_t __reserved_2 : 29;
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#else /* __BIG_ENDIAN__ */
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uint_reg_t __reserved_2 : 29;
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uint_reg_t wfifo_count : 3;
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uint_reg_t __reserved_1 : 7;
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uint_reg_t tfifo_count : 9;
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uint_reg_t __reserved_0 : 7;
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uint_reg_t rfifo_count : 9;
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#endif
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};
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uint_reg_t word;
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} UART_FIFO_COUNT_t;
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/* FLAG. */
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__extension__
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typedef union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/* Reserved. */
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uint_reg_t __reserved_0 : 1;
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/* 1: receive FIFO is empty */
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uint_reg_t rfifo_empty : 1;
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/* 1: write FIFO is empty. */
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uint_reg_t wfifo_empty : 1;
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/* 1: transmit FIFO is empty. */
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uint_reg_t tfifo_empty : 1;
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/* 1: receive FIFO is full. */
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uint_reg_t rfifo_full : 1;
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/* 1: write FIFO is full. */
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uint_reg_t wfifo_full : 1;
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/* 1: transmit FIFO is full. */
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uint_reg_t tfifo_full : 1;
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/* Reserved. */
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uint_reg_t __reserved_1 : 57;
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#else /* __BIG_ENDIAN__ */
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uint_reg_t __reserved_1 : 57;
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uint_reg_t tfifo_full : 1;
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uint_reg_t wfifo_full : 1;
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uint_reg_t rfifo_full : 1;
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uint_reg_t tfifo_empty : 1;
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uint_reg_t wfifo_empty : 1;
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uint_reg_t rfifo_empty : 1;
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uint_reg_t __reserved_0 : 1;
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#endif
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};
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uint_reg_t word;
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} UART_FLAG_t;
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/*
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* Interrupt Vector Mask.
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* Each bit in this register corresponds to a specific interrupt. When set,
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* the associated interrupt will not be dispatched.
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*/
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__extension__
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typedef union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/* Read data FIFO read and no data available */
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uint_reg_t rdat_err : 1;
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/* Write FIFO was written but it was full */
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uint_reg_t wdat_err : 1;
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/* Stop bit not found when current data was received */
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uint_reg_t frame_err : 1;
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/* Parity error was detected when current data was received */
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uint_reg_t parity_err : 1;
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/* Data was received but the receive FIFO was full */
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uint_reg_t rfifo_overflow : 1;
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/*
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* An almost full event is reached when data is to be written to the
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* receive FIFO, and the receive FIFO has more than or equal to
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* BUFFER_THRESHOLD.RFIFO_AFULL bytes.
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*/
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uint_reg_t rfifo_afull : 1;
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/* Reserved. */
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uint_reg_t __reserved_0 : 1;
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/* An entry in the transmit FIFO was popped */
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uint_reg_t tfifo_re : 1;
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/* An entry has been pushed into the receive FIFO */
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uint_reg_t rfifo_we : 1;
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/* An entry of the write FIFO has been popped */
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uint_reg_t wfifo_re : 1;
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/* Rshim read receive FIFO in protocol mode */
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uint_reg_t rfifo_err : 1;
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/*
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* An almost empty event is reached when data is to be read from the
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* transmit FIFO, and the transmit FIFO has less than or equal to
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* BUFFER_THRESHOLD.TFIFO_AEMPTY bytes.
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*/
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uint_reg_t tfifo_aempty : 1;
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/* Reserved. */
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uint_reg_t __reserved_1 : 52;
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#else /* __BIG_ENDIAN__ */
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uint_reg_t __reserved_1 : 52;
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uint_reg_t tfifo_aempty : 1;
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uint_reg_t rfifo_err : 1;
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uint_reg_t wfifo_re : 1;
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uint_reg_t rfifo_we : 1;
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uint_reg_t tfifo_re : 1;
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uint_reg_t __reserved_0 : 1;
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uint_reg_t rfifo_afull : 1;
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uint_reg_t rfifo_overflow : 1;
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uint_reg_t parity_err : 1;
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uint_reg_t frame_err : 1;
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uint_reg_t wdat_err : 1;
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uint_reg_t rdat_err : 1;
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#endif
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};
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uint_reg_t word;
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} UART_INTERRUPT_MASK_t;
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/*
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* Interrupt vector, write-one-to-clear.
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* Each bit in this register corresponds to a specific interrupt. Hardware
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* sets the bit when the associated condition has occurred. Writing a 1
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* clears the status bit.
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*/
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__extension__
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typedef union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/* Read data FIFO read and no data available */
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uint_reg_t rdat_err : 1;
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/* Write FIFO was written but it was full */
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uint_reg_t wdat_err : 1;
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/* Stop bit not found when current data was received */
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uint_reg_t frame_err : 1;
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/* Parity error was detected when current data was received */
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uint_reg_t parity_err : 1;
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/* Data was received but the receive FIFO was full */
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uint_reg_t rfifo_overflow : 1;
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/*
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* Data was received and the receive FIFO is now almost full (more than
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* BUFFER_THRESHOLD.RFIFO_AFULL bytes in it)
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*/
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uint_reg_t rfifo_afull : 1;
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/* Reserved. */
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uint_reg_t __reserved_0 : 1;
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/* An entry in the transmit FIFO was popped */
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uint_reg_t tfifo_re : 1;
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/* An entry has been pushed into the receive FIFO */
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uint_reg_t rfifo_we : 1;
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/* An entry of the write FIFO has been popped */
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uint_reg_t wfifo_re : 1;
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/* Rshim read receive FIFO in protocol mode */
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uint_reg_t rfifo_err : 1;
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/*
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* Data was read from the transmit FIFO and now it is almost empty (less
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* than or equal to BUFFER_THRESHOLD.TFIFO_AEMPTY bytes in it).
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*/
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uint_reg_t tfifo_aempty : 1;
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/* Reserved. */
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uint_reg_t __reserved_1 : 52;
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#else /* __BIG_ENDIAN__ */
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uint_reg_t __reserved_1 : 52;
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uint_reg_t tfifo_aempty : 1;
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uint_reg_t rfifo_err : 1;
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uint_reg_t wfifo_re : 1;
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uint_reg_t rfifo_we : 1;
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uint_reg_t tfifo_re : 1;
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uint_reg_t __reserved_0 : 1;
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uint_reg_t rfifo_afull : 1;
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uint_reg_t rfifo_overflow : 1;
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uint_reg_t parity_err : 1;
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uint_reg_t frame_err : 1;
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uint_reg_t wdat_err : 1;
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uint_reg_t rdat_err : 1;
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#endif
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};
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uint_reg_t word;
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} UART_INTERRUPT_STATUS_t;
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/* Type. */
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__extension__
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typedef union
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{
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struct
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{
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#ifndef __BIG_ENDIAN__
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/* Number of stop bits, rx and tx */
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uint_reg_t sbits : 1;
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/* Reserved. */
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uint_reg_t __reserved_0 : 1;
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/* Data word size, rx and tx */
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uint_reg_t dbits : 1;
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/* Reserved. */
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uint_reg_t __reserved_1 : 1;
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/* Parity selection, rx and tx */
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uint_reg_t ptype : 3;
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/* Reserved. */
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uint_reg_t __reserved_2 : 57;
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#else /* __BIG_ENDIAN__ */
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uint_reg_t __reserved_2 : 57;
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uint_reg_t ptype : 3;
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uint_reg_t __reserved_1 : 1;
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uint_reg_t dbits : 1;
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uint_reg_t __reserved_0 : 1;
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uint_reg_t sbits : 1;
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#endif
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};
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uint_reg_t word;
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} UART_TYPE_t;
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#endif /* !defined(__ASSEMBLER__) */
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#endif /* !defined(__ARCH_UART_H__) */
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