160 lines
5.1 KiB
C
160 lines
5.1 KiB
C
/*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef MSI_H
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#define MSI_H
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#include <asm/msi.h>
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/*
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* Assume the maximum number of hot plug slots supported by the system is about
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* ten. The worstcase is that each of these slots is hot-added with a device,
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* which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
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* attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
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* as below to ensure at least one message is assigned to each detected MSI/
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* MSI-X device function.
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*/
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#define NR_HP_RESERVED_VECTORS 20
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extern int vector_irq[NR_VECTORS];
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extern cpumask_t pending_irq_balance_cpumask[NR_IRQS];
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extern void (*interrupt[NR_IRQS])(void);
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extern int pci_vector_resources(int last, int nr_released);
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#ifdef CONFIG_SMP
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#define set_msi_irq_affinity set_msi_affinity
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#else
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#define set_msi_irq_affinity NULL
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#endif
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#ifndef CONFIG_IRQBALANCE
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static inline void move_msi(int vector) {}
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#endif
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/*
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* MSI-X Address Register
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*/
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF
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#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
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#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
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#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
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#define PCI_MSIX_ENTRY_DATA_OFFSET 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
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#define PCI_MSIX_ENTRY_SIZE 16
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#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
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#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
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#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
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#define msi_data_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
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#define msi_mask_bits_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
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#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
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#define multi_msi_capable(control) \
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(1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
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#define multi_msi_enable(control, num) \
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control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
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#define is_64bit_address(control) (control & PCI_MSI_FLAGS_64BIT)
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#define is_mask_bit_support(control) (control & PCI_MSI_FLAGS_MASKBIT)
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#define msi_enable(control, num) multi_msi_enable(control, num); \
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control |= PCI_MSI_FLAGS_ENABLE
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#define msix_control_reg msi_control_reg
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#define msix_table_offset_reg(base) (base + 0x04)
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#define msix_pba_offset_reg(base) (base + 0x08)
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#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
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#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
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#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
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#define multi_msix_capable msix_table_size
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#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
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#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
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#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
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/*
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* MSI Defined Data Structures
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*/
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#define MSI_ADDRESS_HEADER 0xfee
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#define MSI_ADDRESS_HEADER_SHIFT 12
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#define MSI_ADDRESS_HEADER_MASK 0xfff000
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#define MSI_ADDRESS_DEST_ID_MASK 0xfff0000f
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#define MSI_TARGET_CPU_MASK 0xff
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#define MSI_DELIVERY_MODE 0
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#define MSI_LEVEL_MODE 1 /* Edge always assert */
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#define MSI_TRIGGER_MODE 0 /* MSI is edge sensitive */
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#define MSI_PHYSICAL_MODE 0
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#define MSI_LOGICAL_MODE 1
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#define MSI_REDIRECTION_HINT_MODE 0
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struct msg_data {
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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__u32 vector : 8;
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__u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
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__u32 reserved_1 : 3;
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__u32 level : 1; /* 0: deassert | 1: assert */
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__u32 trigger : 1; /* 0: edge | 1: level */
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__u32 reserved_2 : 16;
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#elif defined(__BIG_ENDIAN_BITFIELD)
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__u32 reserved_2 : 16;
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__u32 trigger : 1; /* 0: edge | 1: level */
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__u32 level : 1; /* 0: deassert | 1: assert */
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__u32 reserved_1 : 3;
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__u32 delivery_mode : 3; /* 000b: FIXED | 001b: lowest prior */
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__u32 vector : 8;
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#else
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#error "Bitfield endianness not defined! Check your byteorder.h"
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#endif
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} __attribute__ ((packed));
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struct msg_address {
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union {
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struct {
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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__u32 reserved_1 : 2;
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__u32 dest_mode : 1; /*0:physic | 1:logic */
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__u32 redirection_hint: 1; /*0: dedicated CPU
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1: lowest priority */
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__u32 reserved_2 : 4;
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__u32 dest_id : 24; /* Destination ID */
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#elif defined(__BIG_ENDIAN_BITFIELD)
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__u32 dest_id : 24; /* Destination ID */
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__u32 reserved_2 : 4;
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__u32 redirection_hint: 1; /*0: dedicated CPU
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1: lowest priority */
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__u32 dest_mode : 1; /*0:physic | 1:logic */
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__u32 reserved_1 : 2;
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#else
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#error "Bitfield endianness not defined! Check your byteorder.h"
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#endif
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}u;
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__u32 value;
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}lo_address;
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__u32 hi_address;
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} __attribute__ ((packed));
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struct msi_desc {
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struct {
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__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
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__u8 maskbit : 1; /* mask-pending bit supported ? */
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__u8 state : 1; /* {0: free, 1: busy} */
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__u8 reserved: 1; /* reserved */
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__u8 entry_nr; /* specific enabled entry */
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__u8 default_vector; /* default pre-assigned vector */
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__u8 current_cpu; /* current destination cpu */
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}msi_attrib;
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struct {
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__u16 head;
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__u16 tail;
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}link;
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void __iomem *mask_base;
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struct pci_dev *dev;
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};
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#endif /* MSI_H */
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