287 lines
6.9 KiB
C
287 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 NXP
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*
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* Clock driver for LS1028A Display output interfaces(LCD, DPHY).
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/bitfield.h>
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/* PLLDIG register offsets and bit masks */
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#define PLLDIG_REG_PLLSR 0x24
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#define PLLDIG_LOCK_MASK BIT(2)
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#define PLLDIG_REG_PLLDV 0x28
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#define PLLDIG_MFD_MASK GENMASK(7, 0)
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#define PLLDIG_RFDPHI1_MASK GENMASK(30, 25)
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#define PLLDIG_REG_PLLFM 0x2c
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#define PLLDIG_SSCGBYP_ENABLE BIT(30)
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#define PLLDIG_REG_PLLFD 0x30
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#define PLLDIG_FDEN BIT(30)
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#define PLLDIG_FRAC_MASK GENMASK(15, 0)
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#define PLLDIG_REG_PLLCAL1 0x38
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#define PLLDIG_REG_PLLCAL2 0x3c
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/* Range of the VCO frequencies, in Hz */
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#define PLLDIG_MIN_VCO_FREQ 650000000
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#define PLLDIG_MAX_VCO_FREQ 1300000000
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/* Range of the output frequencies, in Hz */
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#define PHI1_MIN_FREQ 27000000UL
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#define PHI1_MAX_FREQ 600000000UL
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/* Maximum value of the reduced frequency divider */
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#define MAX_RFDPHI1 63UL
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/* Best value of multiplication factor divider */
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#define PLLDIG_DEFAULT_MFD 44
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/*
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* Denominator part of the fractional part of the
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* loop multiplication factor.
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*/
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#define MFDEN 20480
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static const struct clk_parent_data parent_data[] = {
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{ .index = 0 },
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};
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struct clk_plldig {
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struct clk_hw hw;
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void __iomem *regs;
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unsigned int vco_freq;
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};
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#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw)
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static int plldig_enable(struct clk_hw *hw)
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{
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struct clk_plldig *data = to_clk_plldig(hw);
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u32 val;
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val = readl(data->regs + PLLDIG_REG_PLLFM);
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/*
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* Use Bypass mode with PLL off by default, the frequency overshoot
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* detector output was disable. SSCG Bypass mode should be enable.
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*/
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val |= PLLDIG_SSCGBYP_ENABLE;
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writel(val, data->regs + PLLDIG_REG_PLLFM);
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return 0;
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}
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static void plldig_disable(struct clk_hw *hw)
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{
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struct clk_plldig *data = to_clk_plldig(hw);
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u32 val;
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val = readl(data->regs + PLLDIG_REG_PLLFM);
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val &= ~PLLDIG_SSCGBYP_ENABLE;
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val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0);
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writel(val, data->regs + PLLDIG_REG_PLLFM);
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}
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static int plldig_is_enabled(struct clk_hw *hw)
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{
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struct clk_plldig *data = to_clk_plldig(hw);
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return readl(data->regs + PLLDIG_REG_PLLFM) &
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PLLDIG_SSCGBYP_ENABLE;
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}
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static unsigned long plldig_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_plldig *data = to_clk_plldig(hw);
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u32 val, rfdphi1;
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val = readl(data->regs + PLLDIG_REG_PLLDV);
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/* Check if PLL is bypassed */
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if (val & PLLDIG_SSCGBYP_ENABLE)
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return parent_rate;
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rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val);
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/*
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* If RFDPHI1 has a value of 1 the VCO frequency is also divided by
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* one.
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*/
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if (!rfdphi1)
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rfdphi1 = 1;
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return DIV_ROUND_UP(data->vco_freq, rfdphi1);
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}
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static unsigned long plldig_calc_target_div(unsigned long vco_freq,
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unsigned long target_rate)
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{
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unsigned long div;
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div = DIV_ROUND_CLOSEST(vco_freq, target_rate);
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div = clamp(div, 1UL, MAX_RFDPHI1);
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return div;
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}
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static int plldig_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_plldig *data = to_clk_plldig(hw);
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unsigned int div;
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req->rate = clamp(req->rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);
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div = plldig_calc_target_div(data->vco_freq, req->rate);
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req->rate = DIV_ROUND_UP(data->vco_freq, div);
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return 0;
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}
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static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_plldig *data = to_clk_plldig(hw);
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unsigned int val, cond;
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unsigned int rfdphi1;
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rate = clamp(rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);
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rfdphi1 = plldig_calc_target_div(data->vco_freq, rate);
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/* update the divider value */
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val = readl(data->regs + PLLDIG_REG_PLLDV);
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val &= ~PLLDIG_RFDPHI1_MASK;
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val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1);
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writel(val, data->regs + PLLDIG_REG_PLLDV);
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/* waiting for old lock state to clear */
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udelay(200);
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/* Wait until PLL is locked or timeout */
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return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,
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cond & PLLDIG_LOCK_MASK, 0,
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USEC_PER_MSEC);
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}
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static const struct clk_ops plldig_clk_ops = {
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.enable = plldig_enable,
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.disable = plldig_disable,
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.is_enabled = plldig_is_enabled,
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.recalc_rate = plldig_recalc_rate,
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.determine_rate = plldig_determine_rate,
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.set_rate = plldig_set_rate,
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};
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static int plldig_init(struct clk_hw *hw)
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{
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struct clk_plldig *data = to_clk_plldig(hw);
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struct clk_hw *parent = clk_hw_get_parent(hw);
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unsigned long parent_rate;
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unsigned long val;
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unsigned long long lltmp;
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unsigned int mfd, fracdiv = 0;
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if (!parent)
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return -EINVAL;
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parent_rate = clk_hw_get_rate(parent);
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if (data->vco_freq) {
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mfd = data->vco_freq / parent_rate;
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lltmp = data->vco_freq % parent_rate;
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lltmp *= MFDEN;
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do_div(lltmp, parent_rate);
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fracdiv = lltmp;
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} else {
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mfd = PLLDIG_DEFAULT_MFD;
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data->vco_freq = parent_rate * mfd;
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}
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val = FIELD_PREP(PLLDIG_MFD_MASK, mfd);
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writel(val, data->regs + PLLDIG_REG_PLLDV);
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/* Enable fractional divider */
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if (fracdiv) {
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val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv);
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val |= PLLDIG_FDEN;
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writel(val, data->regs + PLLDIG_REG_PLLFD);
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}
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return 0;
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}
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static int plldig_clk_probe(struct platform_device *pdev)
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{
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struct clk_plldig *data;
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struct device *dev = &pdev->dev;
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int ret;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->regs))
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return PTR_ERR(data->regs);
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data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",
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parent_data,
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&plldig_clk_ops,
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0);
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ret = devm_clk_hw_register(dev, &data->hw);
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if (ret) {
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dev_err(dev, "failed to register %s clock\n",
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dev->of_node->name);
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return ret;
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
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&data->hw);
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if (ret) {
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dev_err(dev, "unable to add clk provider\n");
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return ret;
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}
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/*
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* The frequency of the VCO cannot be changed during runtime.
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* Therefore, let the user specify a desired frequency.
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*/
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if (!of_property_read_u32(dev->of_node, "fsl,vco-hz",
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&data->vco_freq)) {
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if (data->vco_freq < PLLDIG_MIN_VCO_FREQ ||
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data->vco_freq > PLLDIG_MAX_VCO_FREQ)
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return -EINVAL;
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}
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return plldig_init(&data->hw);
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}
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static const struct of_device_id plldig_clk_id[] = {
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{ .compatible = "fsl,ls1028a-plldig" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, plldig_clk_id);
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static struct platform_driver plldig_clk_driver = {
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.driver = {
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.name = "plldig-clock",
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.of_match_table = plldig_clk_id,
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},
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.probe = plldig_clk_probe,
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};
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module_platform_driver(plldig_clk_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>");
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MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver");
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