270 lines
7.4 KiB
C
270 lines
7.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Purna Chandra Mandal,<purna.mandal@microchip.com>
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* Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
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*/
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#include <dt-bindings/clock/microchip,pic32-clock.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <asm/traps.h>
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#include "clk-core.h"
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/* FRC Postscaler */
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#define OSC_FRCDIV_MASK 0x07
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#define OSC_FRCDIV_SHIFT 24
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/* SPLL fields */
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#define PLL_ICLK_MASK 0x01
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#define PLL_ICLK_SHIFT 7
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#define DECLARE_PERIPHERAL_CLOCK(__clk_name, __reg, __flags) \
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{ \
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.ctrl_reg = (__reg), \
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.init_data = { \
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.name = (__clk_name), \
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.parent_names = (const char *[]) { \
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"sys_clk" \
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}, \
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.num_parents = 1, \
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.ops = &pic32_pbclk_ops, \
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.flags = (__flags), \
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}, \
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}
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#define DECLARE_REFO_CLOCK(__clkid, __reg) \
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{ \
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.ctrl_reg = (__reg), \
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.init_data = { \
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.name = "refo" #__clkid "_clk", \
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.parent_names = (const char *[]) { \
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"sys_clk", "pb1_clk", "posc_clk", \
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"frc_clk", "lprc_clk", "sosc_clk", \
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"sys_pll", "refi" #__clkid "_clk", \
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"bfrc_clk", \
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}, \
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.num_parents = 9, \
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.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE,\
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.ops = &pic32_roclk_ops, \
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}, \
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.parent_map = (const u32[]) { \
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0, 1, 2, 3, 4, 5, 7, 8, 9 \
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}, \
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}
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static const struct pic32_ref_osc_data ref_clks[] = {
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DECLARE_REFO_CLOCK(1, 0x80),
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DECLARE_REFO_CLOCK(2, 0xa0),
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DECLARE_REFO_CLOCK(3, 0xc0),
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DECLARE_REFO_CLOCK(4, 0xe0),
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DECLARE_REFO_CLOCK(5, 0x100),
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};
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static const struct pic32_periph_clk_data periph_clocks[] = {
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DECLARE_PERIPHERAL_CLOCK("pb1_clk", 0x140, 0),
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DECLARE_PERIPHERAL_CLOCK("pb2_clk", 0x150, CLK_IGNORE_UNUSED),
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DECLARE_PERIPHERAL_CLOCK("pb3_clk", 0x160, 0),
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DECLARE_PERIPHERAL_CLOCK("pb4_clk", 0x170, 0),
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DECLARE_PERIPHERAL_CLOCK("pb5_clk", 0x180, 0),
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DECLARE_PERIPHERAL_CLOCK("pb6_clk", 0x190, 0),
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DECLARE_PERIPHERAL_CLOCK("cpu_clk", 0x1a0, CLK_IGNORE_UNUSED),
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};
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static const struct pic32_sys_clk_data sys_mux_clk = {
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.slew_reg = 0x1c0,
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.slew_div = 2, /* step of div_4 -> div_2 -> no_div */
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.init_data = {
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.name = "sys_clk",
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.parent_names = (const char *[]) {
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"frcdiv_clk", "sys_pll", "posc_clk",
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"sosc_clk", "lprc_clk", "frcdiv_clk",
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},
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.num_parents = 6,
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.ops = &pic32_sclk_ops,
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},
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.parent_map = (const u32[]) {
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0, 1, 2, 4, 5, 7,
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},
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};
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static const struct pic32_sys_pll_data sys_pll = {
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.ctrl_reg = 0x020,
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.status_reg = 0x1d0,
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.lock_mask = BIT(7),
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.init_data = {
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.name = "sys_pll",
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.parent_names = (const char *[]) {
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"spll_mux_clk"
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},
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.num_parents = 1,
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.ops = &pic32_spll_ops,
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},
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};
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static const struct pic32_sec_osc_data sosc_clk = {
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.status_reg = 0x1d0,
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.enable_mask = BIT(1),
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.status_mask = BIT(4),
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.fixed_rate = 32768,
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.init_data = {
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.name = "sosc_clk",
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.parent_names = NULL,
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.ops = &pic32_sosc_ops,
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},
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};
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static int pic32mzda_critical_clks[] = {
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PB2CLK, PB7CLK
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};
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/* PIC32MZDA clock data */
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struct pic32mzda_clk_data {
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struct clk *clks[MAXCLKS];
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struct pic32_clk_common core;
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struct clk_onecell_data onecell_data;
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struct notifier_block failsafe_notifier;
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};
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static int pic32_fscm_nmi(struct notifier_block *nb,
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unsigned long action, void *data)
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{
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struct pic32mzda_clk_data *cd;
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cd = container_of(nb, struct pic32mzda_clk_data, failsafe_notifier);
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/* SYSCLK is now running from BFRCCLK. Report clock failure. */
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if (readl(cd->core.iobase) & BIT(2))
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pr_alert("pic32-clk: FSCM detected clk failure.\n");
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/* TODO: detect reason of failure and recover accordingly */
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return NOTIFY_OK;
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}
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static int pic32mzda_clk_probe(struct platform_device *pdev)
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{
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const char *const pll_mux_parents[] = {"posc_clk", "frc_clk"};
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struct device_node *np = pdev->dev.of_node;
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struct pic32mzda_clk_data *cd;
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struct pic32_clk_common *core;
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struct clk *pll_mux_clk, *clk;
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struct clk **clks;
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int nr_clks, i, ret;
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cd = devm_kzalloc(&pdev->dev, sizeof(*cd), GFP_KERNEL);
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if (!cd)
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return -ENOMEM;
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core = &cd->core;
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core->iobase = of_io_request_and_map(np, 0, of_node_full_name(np));
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if (IS_ERR(core->iobase)) {
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dev_err(&pdev->dev, "pic32-clk: failed to map registers\n");
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return PTR_ERR(core->iobase);
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}
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spin_lock_init(&core->reg_lock);
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core->dev = &pdev->dev;
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clks = &cd->clks[0];
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/* register fixed rate clocks */
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clks[POSCCLK] = clk_register_fixed_rate(&pdev->dev, "posc_clk", NULL,
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0, 24000000);
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clks[FRCCLK] = clk_register_fixed_rate(&pdev->dev, "frc_clk", NULL,
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0, 8000000);
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clks[BFRCCLK] = clk_register_fixed_rate(&pdev->dev, "bfrc_clk", NULL,
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0, 8000000);
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clks[LPRCCLK] = clk_register_fixed_rate(&pdev->dev, "lprc_clk", NULL,
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0, 32000);
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clks[UPLLCLK] = clk_register_fixed_rate(&pdev->dev, "usbphy_clk", NULL,
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0, 24000000);
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/* fixed rate (optional) clock */
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if (of_property_read_bool(np, "microchip,pic32mzda-sosc")) {
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pr_info("pic32-clk: dt requests SOSC.\n");
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clks[SOSCCLK] = pic32_sosc_clk_register(&sosc_clk, core);
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}
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/* divider clock */
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clks[FRCDIVCLK] = clk_register_divider(&pdev->dev, "frcdiv_clk",
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"frc_clk", 0,
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core->iobase,
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OSC_FRCDIV_SHIFT,
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OSC_FRCDIV_MASK,
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CLK_DIVIDER_POWER_OF_TWO,
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&core->reg_lock);
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/* PLL ICLK mux */
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pll_mux_clk = clk_register_mux(&pdev->dev, "spll_mux_clk",
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pll_mux_parents, 2, 0,
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core->iobase + 0x020,
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PLL_ICLK_SHIFT, 1, 0, &core->reg_lock);
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if (IS_ERR(pll_mux_clk))
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pr_err("spll_mux_clk: clk register failed\n");
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/* PLL */
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clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core);
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/* SYSTEM clock */
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clks[SCLK] = pic32_sys_clk_register(&sys_mux_clk, core);
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/* Peripheral bus clocks */
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for (nr_clks = PB1CLK, i = 0; nr_clks <= PB7CLK; i++, nr_clks++)
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clks[nr_clks] = pic32_periph_clk_register(&periph_clocks[i],
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core);
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/* Reference oscillator clock */
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for (nr_clks = REF1CLK, i = 0; nr_clks <= REF5CLK; i++, nr_clks++)
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clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core);
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/* register clkdev */
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for (i = 0; i < MAXCLKS; i++) {
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if (IS_ERR(clks[i]))
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continue;
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clk_register_clkdev(clks[i], NULL, __clk_get_name(clks[i]));
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}
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/* register clock provider */
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cd->onecell_data.clks = clks;
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cd->onecell_data.clk_num = MAXCLKS;
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ret = of_clk_add_provider(np, of_clk_src_onecell_get,
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&cd->onecell_data);
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if (ret)
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return ret;
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/* force enable critical clocks */
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for (i = 0; i < ARRAY_SIZE(pic32mzda_critical_clks); i++) {
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clk = clks[pic32mzda_critical_clks[i]];
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if (clk_prepare_enable(clk))
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dev_err(&pdev->dev, "clk_prepare_enable(%s) failed\n",
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__clk_get_name(clk));
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}
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/* register NMI for failsafe clock monitor */
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cd->failsafe_notifier.notifier_call = pic32_fscm_nmi;
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return register_nmi_notifier(&cd->failsafe_notifier);
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}
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static const struct of_device_id pic32mzda_clk_match_table[] = {
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{ .compatible = "microchip,pic32mzda-clk", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, pic32mzda_clk_match_table);
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static struct platform_driver pic32mzda_clk_driver = {
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.probe = pic32mzda_clk_probe,
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.driver = {
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.name = "clk-pic32mzda",
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.of_match_table = pic32mzda_clk_match_table,
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},
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};
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static int __init microchip_pic32mzda_clk_init(void)
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{
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return platform_driver_register(&pic32mzda_clk_driver);
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}
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core_initcall(microchip_pic32mzda_clk_init);
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MODULE_DESCRIPTION("Microchip PIC32MZDA Clock Driver");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:clk-pic32mzda");
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