161 lines
5.0 KiB
C
161 lines
5.0 KiB
C
/*
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* arch/sh/boards/dreamcast/irq.c
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*
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* Holly IRQ support for the Sega Dreamcast.
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*
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* Copyright (c) 2001, 2002 M. R. Brown <mrbrown@0xd6.org>
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*
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* This file is part of the LinuxDC project (www.linuxdc.org)
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* Released under the terms of the GNU GPL v2.0
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*/
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/dreamcast/sysasic.h>
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/* Dreamcast System ASIC Hardware Events -
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The Dreamcast's System ASIC (a.k.a. Holly) is responsible for receiving
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hardware events from system peripherals and triggering an SH7750 IRQ.
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Hardware events can trigger IRQs 13, 11, or 9 depending on which bits are
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set in the Event Mask Registers (EMRs). When a hardware event is
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triggered, it's corresponding bit in the Event Status Registers (ESRs)
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is set, and that bit should be rewritten to the ESR to acknowledge that
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event.
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There are three 32-bit ESRs located at 0xa05f8900 - 0xa05f6908. Event
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types can be found in include/asm-sh/dc_sysasic.h. There are three groups
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of EMRs that parallel the ESRs. Each EMR group corresponds to an IRQ, so
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0xa05f6910 - 0xa05f6918 triggers IRQ 13, 0xa05f6920 - 0xa05f6928 triggers
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IRQ 11, and 0xa05f6930 - 0xa05f6938 triggers IRQ 9.
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In the kernel, these events are mapped to virtual IRQs so that drivers can
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respond to them as they would a normal interrupt. In order to keep this
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mapping simple, the events are mapped as:
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6900/6910 - Events 0-31, IRQ 13
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6904/6924 - Events 32-63, IRQ 11
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6908/6938 - Events 64-95, IRQ 9
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*/
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#define ESR_BASE 0x005f6900 /* Base event status register */
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#define EMR_BASE 0x005f6910 /* Base event mask register */
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/* Helps us determine the EMR group that this event belongs to: 0 = 0x6910,
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1 = 0x6920, 2 = 0x6930; also determine the event offset */
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#define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)
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/* Return the hardware event's bit positon within the EMR/ESR */
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#define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)
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/* For each of these *_irq routines, the IRQ passed in is the virtual IRQ
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(logically mapped to the corresponding bit for the hardware event). */
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/* Disable the hardware event by masking its bit in its EMR */
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static inline void disable_systemasic_irq(unsigned int irq)
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{
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unsigned long flags;
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__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
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__u32 mask;
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local_irq_save(flags);
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mask = inl(emr);
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mask &= ~(1 << EVENT_BIT(irq));
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outl(mask, emr);
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local_irq_restore(flags);
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}
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/* Enable the hardware event by setting its bit in its EMR */
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static inline void enable_systemasic_irq(unsigned int irq)
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{
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unsigned long flags;
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__u32 emr = EMR_BASE + (LEVEL(irq) << 4) + (LEVEL(irq) << 2);
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__u32 mask;
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local_irq_save(flags);
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mask = inl(emr);
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mask |= (1 << EVENT_BIT(irq));
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outl(mask, emr);
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local_irq_restore(flags);
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}
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/* Acknowledge a hardware event by writing its bit back to its ESR */
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static void ack_systemasic_irq(unsigned int irq)
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{
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__u32 esr = ESR_BASE + (LEVEL(irq) << 2);
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disable_systemasic_irq(irq);
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outl((1 << EVENT_BIT(irq)), esr);
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}
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/* After a IRQ has been ack'd and responded to, it needs to be renabled */
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static void end_systemasic_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_systemasic_irq(irq);
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}
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static unsigned int startup_systemasic_irq(unsigned int irq)
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{
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enable_systemasic_irq(irq);
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return 0;
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}
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static void shutdown_systemasic_irq(unsigned int irq)
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{
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disable_systemasic_irq(irq);
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}
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struct hw_interrupt_type systemasic_int = {
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.typename = "System ASIC",
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.startup = startup_systemasic_irq,
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.shutdown = shutdown_systemasic_irq,
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.enable = enable_systemasic_irq,
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.disable = disable_systemasic_irq,
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.ack = ack_systemasic_irq,
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.end = end_systemasic_irq,
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};
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/*
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* Map the hardware event indicated by the processor IRQ to a virtual IRQ.
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*/
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int systemasic_irq_demux(int irq)
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{
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__u32 emr, esr, status, level;
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__u32 j, bit;
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switch (irq) {
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case 13:
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level = 0;
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break;
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case 11:
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level = 1;
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break;
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case 9:
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level = 2;
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break;
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default:
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return irq;
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}
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emr = EMR_BASE + (level << 4) + (level << 2);
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esr = ESR_BASE + (level << 2);
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/* Mask the ESR to filter any spurious, unwanted interrtupts */
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status = inl(esr);
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status &= inl(emr);
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/* Now scan and find the first set bit as the event to map */
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for (bit = 1, j = 0; j < 32; bit <<= 1, j++) {
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if (status & bit) {
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irq = HW_EVENT_IRQ_BASE + j + (level << 5);
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return irq;
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}
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}
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/* Not reached */
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return irq;
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}
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