199 lines
8.5 KiB
C
199 lines
8.5 KiB
C
/*
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* xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration
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*
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* NOTE: The location and contents of this file are highly subject to change.
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*
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* Source for configuration-independent binaries (which link in a
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* configuration-specific HAL library) must NEVER include this file.
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* The HAL itself has historically included this file in some instances,
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* but this is not appropriate either, because the HAL is meant to be
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* core-specific but system independent.
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*/
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/*
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* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2.1 of the GNU Lesser General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Further, this software is distributed without any warranty that it is
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* free of the rightful claim of any third person regarding infringement
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* or the like. Any license provided herein, whether implied or
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* otherwise, applies only to this software file. Patent licenses, if
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* any, provided herein do not apply to combinations of this program with
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* other software, or any other product whatsoever.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
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* USA.
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*/
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#ifndef XTENSA_CONFIG_SYSTEM_H
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#define XTENSA_CONFIG_SYSTEM_H
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/*#include <xtensa/hal.h>*/
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/*----------------------------------------------------------------------
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DEVICE ADDRESSES
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----------------------------------------------------------------------*/
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/*
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* Strange place to find these, but the configuration GUI
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* allows moving these around to account for various core
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* configurations. Specific boards (and their BSP software)
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* will have specific meanings for these components.
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*/
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/* I/O Block areas: */
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#define XSHAL_IOBLOCK_CACHED_VADDR 0xE0000000
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#define XSHAL_IOBLOCK_CACHED_PADDR 0xF0000000
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#define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000
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#define XSHAL_IOBLOCK_BYPASS_VADDR 0xF0000000
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#define XSHAL_IOBLOCK_BYPASS_PADDR 0xF0000000
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#define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000
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/* System ROM: */
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#define XSHAL_ROM_VADDR 0xEE000000
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#define XSHAL_ROM_PADDR 0xFE000000
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#define XSHAL_ROM_SIZE 0x00400000
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/* Largest available area (free of vectors): */
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#define XSHAL_ROM_AVAIL_VADDR 0xEE00052C
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#define XSHAL_ROM_AVAIL_VSIZE 0x003FFAD4
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/* System RAM: */
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#define XSHAL_RAM_VADDR 0xD0000000
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#define XSHAL_RAM_PADDR 0x00000000
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#define XSHAL_RAM_VSIZE 0x08000000
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#define XSHAL_RAM_PSIZE 0x10000000
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#define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE
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/* Largest available area (free of vectors): */
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#define XSHAL_RAM_AVAIL_VADDR 0xD0000370
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#define XSHAL_RAM_AVAIL_VSIZE 0x07FFFC90
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/*
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* Shadow system RAM (same device as system RAM, at different address).
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* (Emulation boards need this for the SONIC Ethernet driver
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* when data caches are configured for writeback mode.)
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* NOTE: on full MMU configs, this points to the BYPASS virtual address
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* of system RAM, ie. is the same as XSHAL_RAM_* except that virtual
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* addresses are viewed through the BYPASS static map rather than
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* the CACHED static map.
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*/
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#define XSHAL_RAM_BYPASS_VADDR 0xD8000000
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#define XSHAL_RAM_BYPASS_PADDR 0x00000000
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#define XSHAL_RAM_BYPASS_PSIZE 0x08000000
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/* Alternate system RAM (different device than system RAM): */
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#define XSHAL_ALTRAM_VADDR 0xCEE00000
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#define XSHAL_ALTRAM_PADDR 0xC0000000
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#define XSHAL_ALTRAM_SIZE 0x00200000
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/*----------------------------------------------------------------------
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* DEVICE-ADDRESS DEPENDENT...
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*
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* Values written to CACHEATTR special register (or its equivalent)
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* to enable and disable caches in various modes.
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*----------------------------------------------------------------------*/
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/*----------------------------------------------------------------------
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BACKWARD COMPATIBILITY ...
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----------------------------------------------------------------------*/
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/*
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* NOTE: the following two macros are DEPRECATED. Use the latter
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* board-specific macros instead, which are specially tuned for the
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* particular target environments' memory maps.
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*/
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#define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */
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#define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */
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/*----------------------------------------------------------------------
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ISS (Instruction Set Simulator) SPECIFIC ...
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----------------------------------------------------------------------*/
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#define XSHAL_ISS_CACHEATTR_WRITEBACK 0x1122222F /* enable caches in write-back mode */
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#define XSHAL_ISS_CACHEATTR_WRITEALLOC 0x1122222F /* enable caches in write-allocate mode */
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#define XSHAL_ISS_CACHEATTR_WRITETHRU 0x1122222F /* enable caches in write-through mode */
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#define XSHAL_ISS_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */
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#define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_WRITEBACK /* default setting to enable caches */
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/* For Coware only: */
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#define XSHAL_COWARE_CACHEATTR_WRITEBACK 0x11222222 /* enable caches in write-back mode */
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#define XSHAL_COWARE_CACHEATTR_WRITEALLOC 0x11222222 /* enable caches in write-allocate mode */
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#define XSHAL_COWARE_CACHEATTR_WRITETHRU 0x11222222 /* enable caches in write-through mode */
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#define XSHAL_COWARE_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */
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#define XSHAL_COWARE_CACHEATTR_DEFAULT XSHAL_COWARE_CACHEATTR_WRITEBACK /* default setting to enable caches */
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/* For BFM and other purposes: */
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#define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x11222222 /* enable caches without any invalid regions */
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#define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting for caches without any invalid regions */
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#define XSHAL_ISS_PIPE_REGIONS 0
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#define XSHAL_ISS_SDRAM_REGIONS 0
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/*----------------------------------------------------------------------
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XT2000 BOARD SPECIFIC ...
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----------------------------------------------------------------------*/
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#define XSHAL_XT2000_CACHEATTR_WRITEBACK 0x22FFFFFF /* enable caches in write-back mode */
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#define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0x22FFFFFF /* enable caches in write-allocate mode */
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#define XSHAL_XT2000_CACHEATTR_WRITETHRU 0x22FFFFFF /* enable caches in write-through mode */
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#define XSHAL_XT2000_CACHEATTR_BYPASS 0x22FFFFFF /* disable caches in bypass mode */
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#define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */
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#define XSHAL_XT2000_PIPE_REGIONS 0x00001000 /* BusInt pipeline regions */
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#define XSHAL_XT2000_SDRAM_REGIONS 0x00000005 /* BusInt SDRAM regions */
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/*----------------------------------------------------------------------
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VECTOR SIZES
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----------------------------------------------------------------------*/
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/*
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* Sizes allocated to vectors by the system (memory map) configuration.
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* These sizes are constrained by core configuration (eg. one vector's
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* code cannot overflow into another vector) but are dependent on the
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* system or board (or LSP) memory map configuration.
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*
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* Whether or not each vector happens to be in a system ROM is also
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* a system configuration matter, sometimes useful, included here also:
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*/
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#define XSHAL_RESET_VECTOR_SIZE 0x000004E0
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#define XSHAL_RESET_VECTOR_ISROM 1
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#define XSHAL_USER_VECTOR_SIZE 0x0000001C
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#define XSHAL_USER_VECTOR_ISROM 0
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#define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_KERNEL_VECTOR_SIZE 0x0000001C
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#define XSHAL_KERNEL_VECTOR_ISROM 0
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#define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */
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#define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x000000E0
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#define XSHAL_DOUBLEEXC_VECTOR_ISROM 0
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#define XSHAL_WINDOW_VECTORS_SIZE 0x00000180
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#define XSHAL_WINDOW_VECTORS_ISROM 0
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#define XSHAL_INTLEVEL2_VECTOR_SIZE 0x0000000C
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#define XSHAL_INTLEVEL2_VECTOR_ISROM 0
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#define XSHAL_INTLEVEL3_VECTOR_SIZE 0x0000000C
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#define XSHAL_INTLEVEL3_VECTOR_ISROM 0
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#define XSHAL_INTLEVEL4_VECTOR_SIZE 0x0000000C
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#define XSHAL_INTLEVEL4_VECTOR_ISROM 1
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#define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL4_VECTOR_SIZE
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#define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL4_VECTOR_ISROM
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#endif /*XTENSA_CONFIG_SYSTEM_H*/
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