337 lines
11 KiB
Plaintext
337 lines
11 KiB
Plaintext
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PCI Power Management
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~~~~~~~~~~~~~~~~~~~~
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An overview of the concepts and the related functions in the Linux kernel
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Patrick Mochel <mochel@transmeta.com>
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(and others)
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---------------------------------------------------------------------------
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1. Overview
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2. How the PCI Subsystem Does Power Management
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3. PCI Utility Functions
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4. PCI Device Drivers
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5. Resources
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1. Overview
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~~~~~~~~~~~
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The PCI Power Management Specification was introduced between the PCI 2.1 and
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PCI 2.2 Specifications. It a standard interface for controlling various
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power management operations.
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Implementation of the PCI PM Spec is optional, as are several sub-components of
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it. If a device supports the PCI PM Spec, the device will have an 8 byte
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capability field in its PCI configuration space. This field is used to describe
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and control the standard PCI power management features.
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The PCI PM spec defines 4 operating states for devices (D0 - D3) and for buses
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(B0 - B3). The higher the number, the less power the device consumes. However,
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the higher the number, the longer the latency is for the device to return to
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an operational state (D0).
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There are actually two D3 states. When someone talks about D3, they usually
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mean D3hot, which corresponds to an ACPI D2 state (power is reduced, the
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device may lose some context). But they may also mean D3cold, which is an
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ACPI D3 state (power is fully off, all state was discarded); or both.
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Bus power management is not covered in this version of this document.
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Note that all PCI devices support D0 and D3cold by default, regardless of
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whether or not they implement any of the PCI PM spec.
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The possible state transitions that a device can undergo are:
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+---------------------------+
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| Current State | New State |
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+---------------------------+
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| D0 | D1, D2, D3|
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+---------------------------+
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| D1 | D2, D3 |
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+---------------------------+
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| D2 | D3 |
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+---------------------------+
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| D1, D2, D3 | D0 |
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+---------------------------+
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Note that when the system is entering a global suspend state, all devices will
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be placed into D3 and when resuming, all devices will be placed into D0.
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However, when the system is running, other state transitions are possible.
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2. How The PCI Subsystem Handles Power Management
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The PCI suspend/resume functionality is accessed indirectly via the Power
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Management subsystem. At boot, the PCI driver registers a power management
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callback with that layer. Upon entering a suspend state, the PM layer iterates
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through all of its registered callbacks. This currently takes place only during
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APM state transitions.
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Upon going to sleep, the PCI subsystem walks its device tree twice. Both times,
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it does a depth first walk of the device tree. The first walk saves each of the
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device's state and checks for devices that will prevent the system from entering
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a global power state. The next walk then places the devices in a low power
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state.
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The first walk allows a graceful recovery in the event of a failure, since none
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of the devices have actually been powered down.
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In both walks, in particular the second, all children of a bridge are touched
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before the actual bridge itself. This allows the bridge to retain power while
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its children are being accessed.
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Upon resuming from sleep, just the opposite must be true: all bridges must be
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powered on and restored before their children are powered on. This is easily
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accomplished with a breadth-first walk of the PCI device tree.
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3. PCI Utility Functions
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~~~~~~~~~~~~~~~~~~~~~~~~
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These are helper functions designed to be called by individual device drivers.
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Assuming that a device behaves as advertised, these should be applicable in most
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cases. However, results may vary.
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Note that these functions are never implicitly called for the driver. The driver
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is always responsible for deciding when and if to call these.
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pci_save_state
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--------------
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Usage:
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pci_save_state(struct pci_dev *dev);
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Description:
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Save first 64 bytes of PCI config space, along with any additional
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PCI-Express or PCI-X information.
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pci_restore_state
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-----------------
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Usage:
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pci_restore_state(struct pci_dev *dev);
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Description:
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Restore previously saved config space.
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pci_set_power_state
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-------------------
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Usage:
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pci_set_power_state(struct pci_dev *dev, pci_power_t state);
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Description:
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Transition device to low power state using PCI PM Capabilities
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registers.
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Will fail under one of the following conditions:
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- If state is less than current state, but not D0 (illegal transition)
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- Device doesn't support PM Capabilities
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- Device does not support requested state
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pci_enable_wake
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---------------
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Usage:
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pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
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Description:
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Enable device to generate PME# during low power state using PCI PM
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Capabilities.
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Checks whether if device supports generating PME# from requested state
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and fail if it does not, unless enable == 0 (request is to disable wake
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events, which is implicit if it doesn't even support it in the first
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place).
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Note that the PMC Register in the device's PM Capabilities has a bitmask
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of the states it supports generating PME# from. D3hot is bit 3 and
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D3cold is bit 4. So, while a value of 4 as the state may not seem
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semantically correct, it is.
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4. PCI Device Drivers
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~~~~~~~~~~~~~~~~~~~~~
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These functions are intended for use by individual drivers, and are defined in
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struct pci_driver:
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int (*suspend) (struct pci_dev *dev, pm_message_t state);
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int (*resume) (struct pci_dev *dev);
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int (*enable_wake) (struct pci_dev *dev, pci_power_t state, int enable);
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suspend
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-------
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Usage:
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if (dev->driver && dev->driver->suspend)
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dev->driver->suspend(dev,state);
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A driver uses this function to actually transition the device into a low power
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state. This should include disabling I/O, IRQs, and bus-mastering, as well as
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physically transitioning the device to a lower power state; it may also include
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calls to pci_enable_wake().
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Bus mastering may be disabled by doing:
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pci_disable_device(dev);
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For devices that support the PCI PM Spec, this may be used to set the device's
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power state to match the suspend() parameter:
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pci_set_power_state(dev,state);
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The driver is also responsible for disabling any other device-specific features
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(e.g blanking screen, turning off on-card memory, etc).
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The driver should be sure to track the current state of the device, as it may
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obviate the need for some operations.
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The driver should update the current_state field in its pci_dev structure in
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this function, except for PM-capable devices when pci_set_power_state is used.
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resume
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------
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Usage:
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if (dev->driver && dev->driver->resume)
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dev->driver->resume(dev)
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The resume callback may be called from any power state, and is always meant to
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transition the device to the D0 state.
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The driver is responsible for reenabling any features of the device that had
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been disabled during previous suspend calls, such as IRQs and bus mastering,
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as well as calling pci_restore_state().
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If the device is currently in D3, it may need to be reinitialized in resume().
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* Some types of devices, like bus controllers, will preserve context in D3hot
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(using Vcc power). Their drivers will often want to avoid re-initializing
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them after re-entering D0 (perhaps to avoid resetting downstream devices).
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* Other kinds of devices in D3hot will discard device context as part of a
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soft reset when re-entering the D0 state.
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* Devices resuming from D3cold always go through a power-on reset. Some
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device context can also be preserved using Vaux power.
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* Some systems hide D3cold resume paths from drivers. For example, on PCs
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the resume path for suspend-to-disk often runs BIOS powerup code, which
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will sometimes re-initialize the device.
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To handle resets during D3 to D0 transitions, it may be convenient to share
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device initialization code between probe() and resume(). Device parameters
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can also be saved before the driver suspends into D3, avoiding re-probe.
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If the device supports the PCI PM Spec, it can use this to physically transition
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the device to D0:
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pci_set_power_state(dev,0);
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Note that if the entire system is transitioning out of a global sleep state, all
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devices will be placed in the D0 state, so this is not necessary. However, in
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the event that the device is placed in the D3 state during normal operation,
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this call is necessary. It is impossible to determine which of the two events is
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taking place in the driver, so it is always a good idea to make that call.
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The driver should take note of the state that it is resuming from in order to
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ensure correct (and speedy) operation.
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The driver should update the current_state field in its pci_dev structure in
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this function, except for PM-capable devices when pci_set_power_state is used.
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enable_wake
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-----------
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Usage:
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if (dev->driver && dev->driver->enable_wake)
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dev->driver->enable_wake(dev,state,enable);
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This callback is generally only relevant for devices that support the PCI PM
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spec and have the ability to generate a PME# (Power Management Event Signal)
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to wake the system up. (However, it is possible that a device may support
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some non-standard way of generating a wake event on sleep.)
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Bits 15:11 of the PMC (Power Mgmt Capabilities) Register in a device's
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PM Capabilities describe what power states the device supports generating a
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wake event from:
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+------------------+
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| Bit | State |
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+------------------+
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| 11 | D0 |
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| 12 | D1 |
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| 13 | D2 |
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| 14 | D3hot |
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| 15 | D3cold |
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+------------------+
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A device can use this to enable wake events:
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pci_enable_wake(dev,state,enable);
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Note that to enable PME# from D3cold, a value of 4 should be passed to
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pci_enable_wake (since it uses an index into a bitmask). If a driver gets
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a request to enable wake events from D3, two calls should be made to
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pci_enable_wake (one for both D3hot and D3cold).
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A reference implementation
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-------------------------
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.suspend()
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{
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/* driver specific operations */
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/* Disable IRQ */
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free_irq();
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/* If using MSI */
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pci_disable_msi();
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pci_save_state();
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pci_enable_wake();
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/* Disable IO/bus master/irq router */
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pci_disable_device();
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pci_set_power_state(pci_choose_state());
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}
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.resume()
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{
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pci_set_power_state(PCI_D0);
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pci_restore_state();
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/* device's irq possibly is changed, driver should take care */
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pci_enable_device();
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pci_set_master();
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/* if using MSI, device's vector possibly is changed */
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pci_enable_msi();
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request_irq();
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/* driver specific operations; */
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}
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This is a typical implementation. Drivers can slightly change the order
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of the operations in the implementation, ignore some operations or add
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more driver specific operations in it, but drivers should do something like
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this on the whole.
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5. Resources
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~~~~~~~~~~~~
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PCI Local Bus Specification
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PCI Bus Power Management Interface Specification
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http://www.pcisig.com
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