90 lines
2.3 KiB
ArmAsm
90 lines
2.3 KiB
ArmAsm
/*
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* Low-level IRQ helper macros for U8500 platforms
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*
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* Copyright (C) 2009 ST-Ericsson.
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*
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* This file is a copy of ARM Realview platform.
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* -just satisfied checkpatch script.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <asm/hardware/gic.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =IO_ADDRESS(UX500_GIC_CPU_BASE)
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* The interrupt numbering scheme is defined in the
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* interrupt controller spec. To wit:
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*
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* Interrupts 0-15 are IPI
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* 16-28 are reserved
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* 29-31 are local. We allow 30 to be used for the watchdog.
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* 32-1020 are global
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* 1021-1022 are reserved
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* 1023 is "spurious" (no interrupt)
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*
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* For now, we ignore all local interrupts so only return an
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* interrupt if it's between 30 and 1020. The test_for_ipi
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* routine below will pick up on IPIs.
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*
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* A simple read from the controller will tell us the number
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* of the highest priority enabled interrupt. We then just
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* need to check whether it is in the valid range for an
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* IRQ (30-1020 inclusive).
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*/
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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/* bits 12-10 = src CPU, 9-0 = int # */
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ldr \irqstat, [\base, #GIC_CPU_INTACK]
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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.endm
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/* We assume that irqstat (the raw value of the IRQ
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* acknowledge register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of
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* interrupt on the controller, since this requires the
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* original irqstat value which we won't easily be able
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* to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base
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* are preserved..
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*/
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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