334 lines
7.4 KiB
ArmAsm
334 lines
7.4 KiB
ArmAsm
/* -*- mode: asm -*-
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*
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* linux/arch/h8300/platform/h8300h/entry.S
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*
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* Yoshinori Sato <ysato@users.sourceforge.jp>
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* David McCullough <davidm@snapgear.com>
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*
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*/
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/*
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* entry.S
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* include exception/interrupt gateway
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* system call entry
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*/
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#include <linux/sys.h>
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#include <linux/config.h>
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#include <asm/unistd.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/errno.h>
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.h8300h
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/* CPU context save/restore macros. */
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.macro SAVE_ALL
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mov.l er0,@-sp
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stc ccr,r0l /* check kernel mode */
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orc #0x10,ccr
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btst #4,r0l
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bne 5f
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mov.l sp,@SYMBOL_NAME(sw_usp) /* user mode */
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mov.l @sp,er0
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mov.l @SYMBOL_NAME(sw_ksp),sp
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sub.l #(LRET-LORIG),sp /* allocate LORIG - LRET */
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mov.l er0,@-sp
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mov.l er1,@-sp
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mov.l @SYMBOL_NAME(sw_usp),er0
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mov.l @(8:16,er0),er1 /* copy the RET addr */
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mov.l er1,@(LRET-LER1:16,sp)
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mov.w e1,r1 /* e1 highbyte = ccr */
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and #0xef,r1h /* mask mode? flag */
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sub.w r0,r0
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mov.b r1h,r0l
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mov.w r0,@(LCCR-LER1:16,sp) /* copy ccr */
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mov.l @(LORIG-LER1:16,sp),er0
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mov.l er0,@(LER0-LER1:16,sp) /* copy ER0 */
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bra 6f
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5:
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mov.l @sp,er0 /* kernel mode */
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subs #2,sp /* dummy ccr */
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mov.l er0,@-sp
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mov.l er1,@-sp
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mov.w @(LRET-LER1:16,sp),r1 /* copy old ccr */
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mov.b r1h,r1l
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mov.b #0,r1h
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mov.w r1,@(LCCR-LER1:16,sp) /* set ccr */
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6:
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mov.l er2,@-sp
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mov.l er3,@-sp
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mov.l er6,@-sp /* syscall arg #6 */
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mov.l er5,@-sp /* syscall arg #5 */
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mov.l er4,@-sp /* syscall arg #4 */
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.endm
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.macro RESTORE_ALL
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mov.l @sp+,er4
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mov.l @sp+,er5
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mov.l @sp+,er6
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mov.l @sp+,er3
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mov.l @sp+,er2
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mov.w @(LCCR-LER1:16,sp),r0 /* check kernel mode */
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btst #4,r0l
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bne 7f
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orc #0x80,ccr
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mov.l @SYMBOL_NAME(sw_usp),er0
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mov.l @(LER0-LER1:16,sp),er1 /* restore ER0 */
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mov.l er1,@er0
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mov.w @(LCCR-LER1:16,sp),r1 /* restore the RET addr */
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mov.b r1l,r1h
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mov.b @(LRET+1-LER1:16,sp),r1l
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mov.w r1,e1
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mov.w @(LRET+2-LER1:16,sp),r1
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mov.l er1,@(8:16,er0)
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mov.l @sp+,er1
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add.l #(LRET-LER1),sp /* remove LORIG - LRET */
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mov.l sp,@SYMBOL_NAME(sw_ksp)
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mov.l er0,sp
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bra 8f
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7:
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mov.l @sp+,er1
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adds #4,sp
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adds #2,sp
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8:
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mov.l @sp+,er0
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adds #4,sp /* remove the sw created LVEC */
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rte
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.endm
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.globl SYMBOL_NAME(system_call)
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.globl SYMBOL_NAME(ret_from_exception)
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.globl SYMBOL_NAME(ret_from_fork)
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.globl SYMBOL_NAME(ret_from_interrupt)
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.globl SYMBOL_NAME(interrupt_redirect_table)
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.globl SYMBOL_NAME(sw_ksp),SYMBOL_NAME(sw_usp)
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.globl SYMBOL_NAME(resume)
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.globl SYMBOL_NAME(interrupt_redirect_table)
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.globl SYMBOL_NAME(interrupt_entry)
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.globl SYMBOL_NAME(system_call)
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.globl SYMBOL_NAME(trace_break)
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#if defined(CONFIG_ROMKERNEL)
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INTERRUPTS = 64
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.section .int_redirect,"ax"
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SYMBOL_NAME_LABEL(interrupt_redirect_table)
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.rept 7
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.long 0
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.endr
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jsr @SYMBOL_NAME(interrupt_entry) /* NMI */
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jmp @SYMBOL_NAME(system_call) /* TRAPA #0 (System call) */
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.long 0
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.long 0
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jmp @SYMBOL_NAME(trace_break) /* TRAPA #3 (breakpoint) */
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.rept INTERRUPTS-12
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jsr @SYMBOL_NAME(interrupt_entry)
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.endr
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#endif
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#if defined(CONFIG_RAMKERNEL)
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.globl SYMBOL_NAME(interrupt_redirect_table)
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.section .bss
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SYMBOL_NAME_LABEL(interrupt_redirect_table)
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.space 4
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#endif
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.section .text
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.align 2
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SYMBOL_NAME_LABEL(interrupt_entry)
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SAVE_ALL
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mov.w @(LCCR,sp),r0
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btst #4,r0l
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bne 1f
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mov.l @SYMBOL_NAME(sw_usp),er0
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mov.l @(4:16,er0),er0
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bra 2f
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1:
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mov.l @(LVEC,sp),er0
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2:
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#if defined(CONFIG_ROMKERNEL)
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sub.l #SYMBOL_NAME(interrupt_redirect_table),er0
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#endif
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#if defined(CONFIG_RAMKERNEL)
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mov.l @SYMBOL_NAME(interrupt_redirect_table),er1
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sub.l er1,er0
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#endif
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shlr.l er0
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shlr.l er0
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dec.l #1,er0
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mov.l sp,er1
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subs #4,er1 /* adjust ret_pc */
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jsr @SYMBOL_NAME(process_int)
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mov.l @SYMBOL_NAME(irq_stat)+CPUSTAT_SOFTIRQ_PENDING,er0
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beq 1f
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jsr @SYMBOL_NAME(do_softirq)
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1:
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jmp @SYMBOL_NAME(ret_from_interrupt)
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SYMBOL_NAME_LABEL(system_call)
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subs #4,sp /* dummy LVEC */
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SAVE_ALL
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mov.w @(LCCR:16,sp),r1
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bset #4,r1l
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ldc r1l,ccr
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mov.l er0,er4
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mov.l #-ENOSYS,er0
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mov.l er0,@(LER0:16,sp)
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/* save top of frame */
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mov.l sp,er0
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jsr @SYMBOL_NAME(set_esp0)
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cmp.l #NR_syscalls,er4
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bcc SYMBOL_NAME(ret_from_exception):16
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shll.l er4
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shll.l er4
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mov.l #SYMBOL_NAME(sys_call_table),er0
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add.l er4,er0
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mov.l @er0,er4
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beq SYMBOL_NAME(ret_from_exception):16
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mov.l sp,er2
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and.w #0xe000,r2
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mov.b @((TASK_FLAGS+3-(TIF_SYSCALL_TRACE >> 3)):16,er2),r2l
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btst #(TIF_SYSCALL_TRACE & 7),r2l
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bne 1f
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mov.l @(LER1:16,sp),er0
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mov.l @(LER2:16,sp),er1
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mov.l @(LER3:16,sp),er2
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jsr @er4
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mov.l er0,@(LER0:16,sp) /* save the return value */
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#if defined(CONFIG_SYSCALL_PRINT)
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jsr @SYMBOL_NAME(syscall_print)
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#endif
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bra SYMBOL_NAME(ret_from_exception):8
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1:
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jsr SYMBOL_NAME(syscall_trace)
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mov.l @(LER1:16,sp),er0
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mov.l @(LER2:16,sp),er1
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mov.l @(LER3:16,sp),er2
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jsr @er4
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mov.l er0,@(LER0:16,sp) /* save the return value */
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jsr @SYMBOL_NAME(syscall_trace)
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bra SYMBOL_NAME(ret_from_exception):8
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SYMBOL_NAME_LABEL(ret_from_fork)
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mov.l er2,er0
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jsr @SYMBOL_NAME(schedule_tail)
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bra SYMBOL_NAME(ret_from_exception):8
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SYMBOL_NAME_LABEL(reschedule)
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/* save top of frame */
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mov.l sp,er0
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jsr @SYMBOL_NAME(set_esp0)
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jsr @SYMBOL_NAME(schedule)
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SYMBOL_NAME_LABEL(ret_from_exception)
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#if defined(CONFIG_PREEMPT)
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orc #0x80,ccr
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#endif
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SYMBOL_NAME_LABEL(ret_from_interrupt)
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mov.b @(LCCR+1:16,sp),r0l
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btst #4,r0l /* check if returning to kernel */
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bne done:8 /* if so, skip resched, signals */
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andc #0x7f,ccr
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mov.l sp,er4
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and.w #0xe000,r4
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mov.l @(TI_FLAGS:16,er4),er1
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and.l #_TIF_WORK_MASK,er1
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beq done:8
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1:
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mov.l @(TI_FLAGS:16,er4),er1
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btst #TIF_NEED_RESCHED,r1l
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bne SYMBOL_NAME(reschedule):16
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mov.l sp,er0
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subs #4,er0 /* adjust retpc */
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mov.l er2,er1
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jsr @SYMBOL_NAME(do_signal)
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#if defined(CONFIG_PREEMPT)
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bra done:8 /* userspace thoru */
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3:
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btst #4,r0l
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beq done:8 /* userspace thoru */
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4:
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mov.l @(TI_PRE_COUNT:16,er4),er1
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bne done:8
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mov.l @(TI_FLAGS:16,er4),er1
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btst #TIF_NEED_RESCHED,r1l
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beq done:8
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mov.b r0l,r0l
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bpl done:8 /* interrupt off (exception path?) */
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mov.l #PREEMPT_ACTIVE,er1
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mov.l er1,@(TI_PRE_COUNT:16,er4)
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andc #0x7f,ccr
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jsr @SYMBOL_NAME(schedule)
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sub.l er1,er1
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mov.l er1,@(TI_PRE_COUNT:16,er4)
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orc #0x80,ccr
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bra 4b:8
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#endif
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done:
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RESTORE_ALL /* Does RTE */
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SYMBOL_NAME_LABEL(resume)
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/*
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* Beware - when entering resume, offset of tss is in d1,
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* prev (the current task) is in a0, next (the new task)
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* is in a1 and d2.b is non-zero if the mm structure is
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* shared between the tasks, so don't change these
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* registers until their contents are no longer needed.
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*/
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/* save sr */
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sub.w r3,r3
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stc ccr,r3l
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mov.w r3,@(THREAD_CCR+2:16,er0)
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/* disable interrupts */
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orc #0x80,ccr
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mov.l @SYMBOL_NAME(sw_usp),er3
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mov.l er3,@(THREAD_USP:16,er0)
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mov.l sp,@(THREAD_KSP:16,er0)
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/* Skip address space switching if they are the same. */
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/* FIXME: what did we hack out of here, this does nothing! */
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mov.l @(THREAD_USP:16,er1),er0
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mov.l er0,@SYMBOL_NAME(sw_usp)
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mov.l @(THREAD_KSP:16,er1),sp
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/* restore status register */
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mov.w @(THREAD_CCR+2:16,er1),r3
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ldc r3l,ccr
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rts
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SYMBOL_NAME_LABEL(trace_break)
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subs #4,sp
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SAVE_ALL
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sub.l er1,er1
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dec.l #1,er1
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mov.l er1,@(LORIG,sp)
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mov.l sp,er0
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jsr @SYMBOL_NAME(set_esp0)
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mov.l @SYMBOL_NAME(sw_usp),er0
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mov.l @er0,er1
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subs #2,er1
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mov.l er1,@er0
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and.w #0xff,e1
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mov.l er1,er0
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jsr @SYMBOL_NAME(trace_trap)
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jmp @SYMBOL_NAME(ret_from_exception)
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.section .bss
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SYMBOL_NAME_LABEL(sw_ksp)
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.space 4
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SYMBOL_NAME_LABEL(sw_usp)
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.space 4
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