f12d0d7c77
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:
Related operation Safe condition
a. any CP15 access !CPU_CP15
b. alignment trap CPU_CP15_MMU
c. D-cache(C-bit) CPU_CP15
d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
CPU_ARM720 || CPU_ARM740 ||
CPU_XSCALE || CPU_XSC3 )
e. alternate vector CPU_CP15 && !CPU_ARM740
f. TTB CPU_CP15_MMU
g. Domain CPU_CP15_MMU
h. FSR/FAR CPU_CP15_MMU
For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
|
||
|---|---|---|
| .. | ||
| Makefile | ||
| Makefile.debug | ||
| big-endian.S | ||
| head-at91rm9200.S | ||
| head-clps7500.S | ||
| head-l7200.S | ||
| head-sa1100.S | ||
| head-shark.S | ||
| head-sharpsl.S | ||
| head-xscale.S | ||
| head.S | ||
| ll_char_wr.S | ||
| misc.c | ||
| ofw-shark.c | ||
| piggy.S | ||
| vmlinux.lds.in | ||