230 lines
6.0 KiB
C
230 lines
6.0 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/tty.h>
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#ifdef CONFIG_MTD
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/physmap.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#endif
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/irq.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/prom.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/dma.h>
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#include <asm/time.h>
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#include <asm/traps.h>
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#ifdef CONFIG_VT
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#include <linux/console.h>
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#endif
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extern void mips_reboot_setup(void);
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extern void mips_time_init(void);
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extern void mips_timer_setup(struct irqaction *irq);
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extern unsigned long mips_rtc_get_time(void);
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#ifdef CONFIG_KGDB
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extern void kgdb_config(void);
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#endif
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struct resource standard_io_resources[] = {
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{ "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
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{ "timer", 0x40, 0x5f, IORESOURCE_BUSY },
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{ "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
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{ "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
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{ "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
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};
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#ifdef CONFIG_MTD
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static struct mtd_partition malta_mtd_partitions[] = {
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{
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.name = "YAMON",
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.offset = 0x0,
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.size = 0x100000,
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.mask_flags = MTD_WRITEABLE
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},
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{
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.name = "User FS",
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.offset = 0x100000,
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.size = 0x2e0000
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},
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{
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.name = "Board Config",
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.offset = 0x3e0000,
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.size = 0x020000,
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.mask_flags = MTD_WRITEABLE
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}
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};
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#define number_partitions (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
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#endif
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const char *get_system_type(void)
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{
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return "MIPS Malta";
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}
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#ifdef CONFIG_BLK_DEV_FD
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void __init fd_activate(void)
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{
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/*
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* Activate Floppy Controller in the SMSC FDC37M817 Super I/O
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* Controller.
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* Done by YAMON 2.00 onwards
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*/
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/* Entering config state. */
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SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
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/* Activate floppy controller. */
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SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
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SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
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SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
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SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
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/* Exit config state. */
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SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
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}
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#endif
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void __init plat_setup(void)
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{
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unsigned int i;
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mips_pcibios_init();
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/* Request I/O space for devices used on the Malta board. */
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for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
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request_resource(&ioport_resource, standard_io_resources+i);
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/*
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* Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
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*/
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enable_dma(4);
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#ifdef CONFIG_KGDB
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kgdb_config ();
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#endif
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if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
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(mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
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(mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
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char *argptr;
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argptr = prom_getcmdline();
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if (strstr(argptr, "debug")) {
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BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
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printk ("Enabled Bonito debug mode\n");
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}
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else
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BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
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#ifdef CONFIG_DMA_COHERENT
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if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
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printk("Enabled Bonito CPU coherency\n");
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argptr = prom_getcmdline();
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if (strstr(argptr, "iobcuncached")) {
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BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
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~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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printk("Disabled Bonito IOBC coherency\n");
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}
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else {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG |=
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(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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printk("Disabled Bonito IOBC coherency\n");
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}
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}
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else
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panic("Hardware DMA cache coherency not supported");
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#endif
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}
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#ifdef CONFIG_DMA_COHERENT
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else {
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panic("Hardware DMA cache coherency not supported");
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}
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#endif
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#ifdef CONFIG_BLK_DEV_IDE
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/* Check PCI clock */
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{
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int jmpr = (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG, sizeof(unsigned int))) >> 2) & 0x07;
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static const int pciclocks[] __initdata = {
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33, 20, 25, 30, 12, 16, 37, 10
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};
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int pciclock = pciclocks[jmpr];
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char *argptr = prom_getcmdline();
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if (pciclock != 33 && !strstr (argptr, "idebus=")) {
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printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
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argptr += strlen(argptr);
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sprintf (argptr, " idebus=%d", pciclock);
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if (pciclock < 20 || pciclock > 66)
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printk ("WARNING: IDE timing calculations will be incorrect\n");
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}
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}
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#endif
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#ifdef CONFIG_BLK_DEV_FD
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fd_activate ();
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#endif
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#ifdef CONFIG_VT
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#if defined(CONFIG_VGA_CONSOLE)
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screen_info = (struct screen_info) {
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0, 25, /* orig-x, orig-y */
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0, /* unused */
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0, /* orig-video-page */
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0, /* orig-video-mode */
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80, /* orig-video-cols */
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0,0,0, /* ega_ax, ega_bx, ega_cx */
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25, /* orig-video-lines */
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VIDEO_TYPE_VGAC, /* orig-video-isVGA */
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16 /* orig-video-points */
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};
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#endif
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#endif
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#ifdef CONFIG_MTD
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/*
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* Support for MTD on Malta. Use the generic physmap driver
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*/
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physmap_configure(0x1e000000, 0x400000, 4, NULL);
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physmap_set_partitions(malta_mtd_partitions, number_partitions);
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#endif
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mips_reboot_setup();
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board_time_init = mips_time_init;
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board_timer_setup = mips_timer_setup;
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rtc_get_time = mips_rtc_get_time;
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}
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