270 lines
6.0 KiB
Plaintext
270 lines
6.0 KiB
Plaintext
/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-msm8996.h>
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#include <dt-bindings/clock/qcom,mmcc-msm8996.h>
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/ {
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model = "Qualcomm Technologies, Inc. MSM8996";
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU1: cpu@1 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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CPU2: cpu@100 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x100>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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L2_1: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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};
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};
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CPU3: cpu@101 {
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device_type = "cpu";
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compatible = "qcom,kryo";
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reg = <0x0 0x101>;
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enable-method = "psci";
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next-level-cache = <&L2_1>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU2>;
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};
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core1 {
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cpu = <&CPU3>;
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};
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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clocks {
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xo_board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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clock-output-names = "xo_board";
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};
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sleep_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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intc: interrupt-controller@9bc0000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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#redistributor-regions = <1>;
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redistributor-stride = <0x0 0x40000>;
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reg = <0x09bc0000 0x10000>,
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<0x09c00000 0x100000>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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gcc: clock-controller@300000 {
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compatible = "qcom,gcc-msm8996";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x300000 0x90000>;
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};
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blsp2_uart1: serial@75b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x75b0000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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pinctrl@1010000 {
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compatible = "qcom,msm8996-pinctrl";
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reg = <0x01010000 0x300000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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timer@09840000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x09840000 0x1000>;
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clock-frequency = <19200000>;
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frame@9850000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09850000 0x1000>,
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<0x09860000 0x1000>;
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};
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frame@9870000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09870000 0x1000>;
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status = "disabled";
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};
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frame@9880000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09880000 0x1000>;
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status = "disabled";
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};
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frame@9890000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x09890000 0x1000>;
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status = "disabled";
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};
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frame@98a0000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x098a0000 0x1000>;
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status = "disabled";
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};
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frame@98b0000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x098b0000 0x1000>;
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status = "disabled";
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};
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frame@98c0000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x098c0000 0x1000>;
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status = "disabled";
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};
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};
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spmi_bus: qcom,spmi@400f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x400f000 0x1000>,
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<0x4400000 0x800000>,
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<0x4c00000 0x800000>,
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<0x5800000 0x200000>,
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<0x400a000 0x002100>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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};
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mmcc: clock-controller@8c0000 {
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compatible = "qcom,mmcc-msm8996";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x8c0000 0x40000>;
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assigned-clocks = <&mmcc MMPLL9_PLL>,
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<&mmcc MMPLL1_PLL>,
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<&mmcc MMPLL3_PLL>,
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<&mmcc MMPLL4_PLL>,
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<&mmcc MMPLL5_PLL>;
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assigned-clock-rates = <624000000>,
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<810000000>,
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<980000000>,
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<960000000>,
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<825000000>;
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};
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};
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};
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