329 lines
7.6 KiB
C
329 lines
7.6 KiB
C
/*
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* intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
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*
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* Copyright (C) 2016 Intel Corp
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* Authors: Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
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* Ramesh Babu K V <ramesh.babu@intel.com>
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* Vaibhav Agarwal <vaibhav.agarwal@intel.com>
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* Jerome Anand <jerome.anand@intel.com>
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* Aravind Siddappaji <aravindx.siddappaji@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#ifndef __INTEL_HDMI_LPE_AUDIO_H
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#define __INTEL_HDMI_LPE_AUDIO_H
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#define HAD_MIN_CHANNEL 2
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#define HAD_MAX_CHANNEL 8
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#define HAD_NUM_OF_RING_BUFS 4
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/* max 20bit address, aligned to 64 */
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#define HAD_MAX_BUFFER ((1024 * 1024 - 1) & ~0x3f)
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#define HAD_DEFAULT_BUFFER (600 * 1024) /* default prealloc size */
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#define HAD_MAX_PERIODS 256 /* arbitrary, but should suffice */
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#define HAD_MIN_PERIODS 1
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#define HAD_MAX_PERIOD_BYTES ((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f)
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#define HAD_MIN_PERIOD_BYTES 1024 /* might be smaller */
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#define HAD_FIFO_SIZE 0 /* fifo not being used */
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#define MAX_SPEAKERS 8
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#define AUD_SAMPLE_RATE_32 32000
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#define AUD_SAMPLE_RATE_44_1 44100
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#define AUD_SAMPLE_RATE_48 48000
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#define AUD_SAMPLE_RATE_88_2 88200
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#define AUD_SAMPLE_RATE_96 96000
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#define AUD_SAMPLE_RATE_176_4 176400
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#define AUD_SAMPLE_RATE_192 192000
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#define HAD_MIN_RATE AUD_SAMPLE_RATE_32
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#define HAD_MAX_RATE AUD_SAMPLE_RATE_192
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#define DIS_SAMPLE_RATE_25_2 25200
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#define DIS_SAMPLE_RATE_27 27000
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#define DIS_SAMPLE_RATE_54 54000
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#define DIS_SAMPLE_RATE_74_25 74250
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#define DIS_SAMPLE_RATE_148_5 148500
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#define HAD_REG_WIDTH 0x08
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#define HAD_MAX_DIP_WORDS 16
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/* DP Link Rates */
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#define DP_2_7_GHZ 270000
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#define DP_1_62_GHZ 162000
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/* Maud Values */
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#define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL 1988
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#define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL 2740
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#define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL 2982
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#define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL 5480
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#define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL 5965
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#define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL 10961
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#define HAD_MAX_RATE_DP_2_7_MAUD_VAL 11930
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#define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL 3314
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#define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL 4567
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#define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL 4971
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#define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL 9134
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#define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL 9942
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#define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL 18268
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#define HAD_MAX_RATE_DP_1_62_MAUD_VAL 19884
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/* Naud Value */
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#define DP_NAUD_VAL 32768
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/* HDMI Controller register offsets - audio domain common */
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/* Base address for below regs = 0x65000 */
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enum hdmi_ctrl_reg_offset_common {
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AUDIO_HDMI_CONFIG_A = 0x000,
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AUDIO_HDMI_CONFIG_B = 0x800,
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AUDIO_HDMI_CONFIG_C = 0x900,
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};
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/* HDMI controller register offsets */
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enum hdmi_ctrl_reg_offset {
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AUD_CONFIG = 0x0,
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AUD_CH_STATUS_0 = 0x08,
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AUD_CH_STATUS_1 = 0x0C,
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AUD_HDMI_CTS = 0x10,
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AUD_N_ENABLE = 0x14,
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AUD_SAMPLE_RATE = 0x18,
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AUD_BUF_CONFIG = 0x20,
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AUD_BUF_CH_SWAP = 0x24,
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AUD_BUF_A_ADDR = 0x40,
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AUD_BUF_A_LENGTH = 0x44,
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AUD_BUF_B_ADDR = 0x48,
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AUD_BUF_B_LENGTH = 0x4c,
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AUD_BUF_C_ADDR = 0x50,
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AUD_BUF_C_LENGTH = 0x54,
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AUD_BUF_D_ADDR = 0x58,
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AUD_BUF_D_LENGTH = 0x5c,
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AUD_CNTL_ST = 0x60,
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AUD_HDMI_STATUS = 0x64, /* v2 */
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AUD_HDMIW_INFOFR = 0x68, /* v2 */
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};
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/* Audio configuration */
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union aud_cfg {
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struct {
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u32 aud_en:1;
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u32 layout:1; /* LAYOUT[01], see below */
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u32 fmt:2;
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u32 num_ch:3;
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u32 set:1;
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u32 flat:1;
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u32 val_bit:1;
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u32 user_bit:1;
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u32 underrun:1; /* 0: send null packets,
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* 1: send silence stream
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*/
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u32 packet_mode:1; /* 0: 32bit container, 1: 16bit */
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u32 left_align:1; /* 0: MSB bits 0-23, 1: bits 8-31 */
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u32 bogus_sample:1; /* bogus sample for odd channels */
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u32 dp_modei:1; /* 0: HDMI, 1: DP */
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u32 rsvd:16;
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} regx;
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u32 regval;
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};
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#define AUD_CONFIG_VALID_BIT (1 << 9)
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#define AUD_CONFIG_DP_MODE (1 << 15)
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#define AUD_CONFIG_CH_MASK 0x70
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#define LAYOUT0 0 /* interleaved stereo */
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#define LAYOUT1 1 /* for channels > 2 */
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/* Audio Channel Status 0 Attributes */
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union aud_ch_status_0 {
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struct {
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u32 ch_status:1;
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u32 lpcm_id:1;
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u32 cp_info:1;
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u32 format:3;
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u32 mode:2;
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u32 ctg_code:8;
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u32 src_num:4;
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u32 ch_num:4;
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u32 samp_freq:4; /* CH_STATUS_MAP_XXX */
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u32 clk_acc:2;
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u32 rsvd:2;
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} regx;
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u32 regval;
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};
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/* samp_freq values - Sampling rate as per IEC60958 Ver 3 */
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#define CH_STATUS_MAP_32KHZ 0x3
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#define CH_STATUS_MAP_44KHZ 0x0
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#define CH_STATUS_MAP_48KHZ 0x2
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#define CH_STATUS_MAP_88KHZ 0x8
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#define CH_STATUS_MAP_96KHZ 0xA
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#define CH_STATUS_MAP_176KHZ 0xC
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#define CH_STATUS_MAP_192KHZ 0xE
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/* Audio Channel Status 1 Attributes */
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union aud_ch_status_1 {
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struct {
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u32 max_wrd_len:1;
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u32 wrd_len:3;
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u32 rsvd:28;
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} regx;
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u32 regval;
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};
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#define MAX_SMPL_WIDTH_20 0x0
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#define MAX_SMPL_WIDTH_24 0x1
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#define SMPL_WIDTH_16BITS 0x1
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#define SMPL_WIDTH_24BITS 0x5
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/* CTS register */
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union aud_hdmi_cts {
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struct {
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u32 cts_val:24;
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u32 en_cts_prog:1;
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u32 rsvd:7;
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} regx;
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u32 regval;
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};
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/* N register */
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union aud_hdmi_n_enable {
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struct {
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u32 n_val:24;
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u32 en_n_prog:1;
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u32 rsvd:7;
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} regx;
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u32 regval;
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};
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/* Audio Buffer configurations */
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union aud_buf_config {
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struct {
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u32 audio_fifo_watermark:8;
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u32 dma_fifo_watermark:3;
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u32 rsvd0:5;
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u32 aud_delay:8;
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u32 rsvd1:8;
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} regx;
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u32 regval;
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};
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#define FIFO_THRESHOLD 0xFE
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#define DMA_FIFO_THRESHOLD 0x7
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/* Audio Sample Swapping offset */
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union aud_buf_ch_swap {
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struct {
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u32 first_0:3;
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u32 second_0:3;
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u32 first_1:3;
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u32 second_1:3;
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u32 first_2:3;
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u32 second_2:3;
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u32 first_3:3;
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u32 second_3:3;
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u32 rsvd:8;
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} regx;
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u32 regval;
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};
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#define SWAP_LFE_CENTER 0x00fac4c8 /* octal 76543210 */
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/* Address for Audio Buffer */
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union aud_buf_addr {
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struct {
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u32 valid:1;
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u32 intr_en:1;
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u32 rsvd:4;
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u32 addr:26;
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} regx;
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u32 regval;
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};
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#define AUD_BUF_VALID (1U << 0)
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#define AUD_BUF_INTR_EN (1U << 1)
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/* Length of Audio Buffer */
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union aud_buf_len {
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struct {
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u32 buf_len:20;
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u32 rsvd:12;
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} regx;
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u32 regval;
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};
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/* Audio Control State Register offset */
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union aud_ctrl_st {
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struct {
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u32 ram_addr:4;
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u32 eld_ack:1;
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u32 eld_addr:4;
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u32 eld_buf_size:5;
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u32 eld_valid:1;
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u32 cp_ready:1;
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u32 dip_freq:2;
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u32 dip_idx:3;
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u32 dip_en_sta:4;
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u32 rsvd:7;
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} regx;
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u32 regval;
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};
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/* Audio HDMI Widget Data Island Packet offset */
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union aud_info_frame1 {
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struct {
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u32 pkt_type:8;
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u32 ver_num:8;
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u32 len:5;
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u32 rsvd:11;
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} regx;
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u32 regval;
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};
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#define HDMI_INFO_FRAME_WORD1 0x000a0184
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#define DP_INFO_FRAME_WORD1 0x00441b84
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/* DIP frame 2 */
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union aud_info_frame2 {
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struct {
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u32 chksum:8;
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u32 chnl_cnt:3;
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u32 rsvd0:1;
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u32 coding_type:4;
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u32 smpl_size:2;
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u32 smpl_freq:3;
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u32 rsvd1:3;
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u32 format:8;
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} regx;
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u32 regval;
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};
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/* DIP frame 3 */
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union aud_info_frame3 {
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struct {
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u32 chnl_alloc:8;
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u32 rsvd0:3;
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u32 lsv:4;
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u32 dm_inh:1;
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u32 rsvd1:16;
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} regx;
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u32 regval;
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};
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#define VALID_DIP_WORDS 3
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/* AUD_HDMI_STATUS bits */
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#define HDMI_AUDIO_UNDERRUN (1U << 31)
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#define HDMI_AUDIO_BUFFER_DONE (1U << 29)
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/* AUD_HDMI_STATUS register mask */
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#define AUD_HDMI_STATUS_MASK_UNDERRUN 0xC0000000
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#define AUD_HDMI_STATUS_MASK_SRDBG 0x00000002
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#define AUD_HDMI_STATUSG_MASK_FUNCRST 0x00000001
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#endif
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