716 lines
19 KiB
C
716 lines
19 KiB
C
/*
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* arch/ppc/kernel/open_pic.c -- OpenPIC Interrupt Handling
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*
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* Copyright (C) 1997 Geert Uytterhoeven
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*
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* This is a duplicate of open_pic.c that deals with U3s MPIC on
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* G5 PowerMacs. It's the same file except it's using big endian
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* register accesses
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/sysdev.h>
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#include <linux/errno.h>
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#include <asm/ptrace.h>
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#include <asm/signal.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/sections.h>
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#include <asm/open_pic.h>
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#include <asm/i8259.h>
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#include "open_pic_defs.h"
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void *OpenPIC2_Addr;
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static volatile struct OpenPIC *OpenPIC2 = NULL;
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/*
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* We define OpenPIC_InitSenses table thusly:
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* bit 0x1: sense, 0 for edge and 1 for level.
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* bit 0x2: polarity, 0 for negative, 1 for positive.
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*/
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extern u_int OpenPIC_NumInitSenses;
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extern u_char *OpenPIC_InitSenses;
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extern int use_of_interrupt_tree;
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static u_int NumProcessors;
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static u_int NumSources;
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static int open_pic2_irq_offset;
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static volatile OpenPIC_Source *ISR[NR_IRQS];
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/* Global Operations */
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static void openpic2_disable_8259_pass_through(void);
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static void openpic2_set_priority(u_int pri);
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static void openpic2_set_spurious(u_int vector);
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/* Timer Interrupts */
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static void openpic2_inittimer(u_int timer, u_int pri, u_int vector);
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static void openpic2_maptimer(u_int timer, u_int cpumask);
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/* Interrupt Sources */
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static void openpic2_enable_irq(u_int irq);
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static void openpic2_disable_irq(u_int irq);
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static void openpic2_initirq(u_int irq, u_int pri, u_int vector, int polarity,
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int is_level);
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static void openpic2_mapirq(u_int irq, u_int cpumask, u_int keepmask);
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/*
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* These functions are not used but the code is kept here
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* for completeness and future reference.
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*/
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static void openpic2_reset(void);
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#ifdef notused
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static void openpic2_enable_8259_pass_through(void);
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static u_int openpic2_get_priority(void);
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static u_int openpic2_get_spurious(void);
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static void openpic2_set_sense(u_int irq, int sense);
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#endif /* notused */
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/*
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* Description of the openpic for the higher-level irq code
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*/
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static void openpic2_end_irq(unsigned int irq_nr);
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static void openpic2_ack_irq(unsigned int irq_nr);
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struct hw_interrupt_type open_pic2 = {
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" OpenPIC2 ",
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NULL,
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NULL,
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openpic2_enable_irq,
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openpic2_disable_irq,
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openpic2_ack_irq,
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openpic2_end_irq,
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};
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/*
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* Accesses to the current processor's openpic registers
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* On cascaded controller, this is only CPU 0
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*/
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#define THIS_CPU Processor[0]
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#define DECL_THIS_CPU
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#define CHECK_THIS_CPU
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#if 1
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#define check_arg_ipi(ipi) \
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if (ipi < 0 || ipi >= OPENPIC_NUM_IPI) \
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printk("open_pic.c:%d: illegal ipi %d\n", __LINE__, ipi);
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#define check_arg_timer(timer) \
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if (timer < 0 || timer >= OPENPIC_NUM_TIMERS) \
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printk("open_pic.c:%d: illegal timer %d\n", __LINE__, timer);
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#define check_arg_vec(vec) \
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if (vec < 0 || vec >= OPENPIC_NUM_VECTORS) \
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printk("open_pic.c:%d: illegal vector %d\n", __LINE__, vec);
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#define check_arg_pri(pri) \
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if (pri < 0 || pri >= OPENPIC_NUM_PRI) \
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printk("open_pic.c:%d: illegal priority %d\n", __LINE__, pri);
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/*
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* Print out a backtrace if it's out of range, since if it's larger than NR_IRQ's
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* data has probably been corrupted and we're going to panic or deadlock later
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* anyway --Troy
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*/
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extern unsigned long* _get_SP(void);
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#define check_arg_irq(irq) \
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if (irq < open_pic2_irq_offset || irq >= NumSources+open_pic2_irq_offset \
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|| ISR[irq - open_pic2_irq_offset] == 0) { \
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printk("open_pic.c:%d: illegal irq %d\n", __LINE__, irq); \
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/*print_backtrace(_get_SP());*/ }
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#define check_arg_cpu(cpu) \
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if (cpu < 0 || cpu >= NumProcessors){ \
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printk("open_pic2.c:%d: illegal cpu %d\n", __LINE__, cpu); \
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/*print_backtrace(_get_SP());*/ }
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#else
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#define check_arg_ipi(ipi) do {} while (0)
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#define check_arg_timer(timer) do {} while (0)
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#define check_arg_vec(vec) do {} while (0)
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#define check_arg_pri(pri) do {} while (0)
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#define check_arg_irq(irq) do {} while (0)
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#define check_arg_cpu(cpu) do {} while (0)
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#endif
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static u_int openpic2_read(volatile u_int *addr)
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{
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u_int val;
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val = in_be32(addr);
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return val;
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}
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static inline void openpic2_write(volatile u_int *addr, u_int val)
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{
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out_be32(addr, val);
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}
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static inline u_int openpic2_readfield(volatile u_int *addr, u_int mask)
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{
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u_int val = openpic2_read(addr);
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return val & mask;
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}
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inline void openpic2_writefield(volatile u_int *addr, u_int mask,
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u_int field)
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{
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u_int val = openpic2_read(addr);
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openpic2_write(addr, (val & ~mask) | (field & mask));
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}
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static inline void openpic2_clearfield(volatile u_int *addr, u_int mask)
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{
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openpic2_writefield(addr, mask, 0);
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}
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static inline void openpic2_setfield(volatile u_int *addr, u_int mask)
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{
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openpic2_writefield(addr, mask, mask);
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}
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static void openpic2_safe_writefield(volatile u_int *addr, u_int mask,
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u_int field)
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{
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openpic2_setfield(addr, OPENPIC_MASK);
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while (openpic2_read(addr) & OPENPIC_ACTIVITY);
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openpic2_writefield(addr, mask | OPENPIC_MASK, field | OPENPIC_MASK);
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}
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static void openpic2_reset(void)
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{
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openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
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OPENPIC_CONFIG_RESET);
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while (openpic2_readfield(&OpenPIC2->Global.Global_Configuration0,
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OPENPIC_CONFIG_RESET))
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mb();
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}
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void __init openpic2_set_sources(int first_irq, int num_irqs, void *first_ISR)
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{
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volatile OpenPIC_Source *src = first_ISR;
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int i, last_irq;
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last_irq = first_irq + num_irqs;
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if (last_irq > NumSources)
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NumSources = last_irq;
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if (src == 0)
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src = &((struct OpenPIC *)OpenPIC2_Addr)->Source[first_irq];
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for (i = first_irq; i < last_irq; ++i, ++src)
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ISR[i] = src;
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}
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/*
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* The `offset' parameter defines where the interrupts handled by the
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* OpenPIC start in the space of interrupt numbers that the kernel knows
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* about. In other words, the OpenPIC's IRQ0 is numbered `offset' in the
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* kernel's interrupt numbering scheme.
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* We assume there is only one OpenPIC.
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*/
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void __init openpic2_init(int offset)
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{
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u_int t, i;
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u_int timerfreq;
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const char *version;
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if (!OpenPIC2_Addr) {
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printk("No OpenPIC2 found !\n");
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return;
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}
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OpenPIC2 = (volatile struct OpenPIC *)OpenPIC2_Addr;
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if (ppc_md.progress) ppc_md.progress("openpic: enter", 0x122);
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t = openpic2_read(&OpenPIC2->Global.Feature_Reporting0);
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switch (t & OPENPIC_FEATURE_VERSION_MASK) {
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case 1:
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version = "1.0";
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break;
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case 2:
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version = "1.2";
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break;
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case 3:
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version = "1.3";
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break;
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default:
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version = "?";
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break;
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}
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NumProcessors = ((t & OPENPIC_FEATURE_LAST_PROCESSOR_MASK) >>
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OPENPIC_FEATURE_LAST_PROCESSOR_SHIFT) + 1;
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if (NumSources == 0)
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openpic2_set_sources(0,
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((t & OPENPIC_FEATURE_LAST_SOURCE_MASK) >>
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OPENPIC_FEATURE_LAST_SOURCE_SHIFT) + 1,
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NULL);
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printk("OpenPIC (2) Version %s (%d CPUs and %d IRQ sources) at %p\n",
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version, NumProcessors, NumSources, OpenPIC2);
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timerfreq = openpic2_read(&OpenPIC2->Global.Timer_Frequency);
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if (timerfreq)
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printk("OpenPIC timer frequency is %d.%06d MHz\n",
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timerfreq / 1000000, timerfreq % 1000000);
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open_pic2_irq_offset = offset;
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/* Initialize timer interrupts */
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if ( ppc_md.progress ) ppc_md.progress("openpic2: timer",0x3ba);
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for (i = 0; i < OPENPIC_NUM_TIMERS; i++) {
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/* Disabled, Priority 0 */
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openpic2_inittimer(i, 0, OPENPIC2_VEC_TIMER+i+offset);
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/* No processor */
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openpic2_maptimer(i, 0);
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}
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/* Initialize external interrupts */
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if (ppc_md.progress) ppc_md.progress("openpic2: external",0x3bc);
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openpic2_set_priority(0xf);
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/* Init all external sources, including possibly the cascade. */
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for (i = 0; i < NumSources; i++) {
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int sense;
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if (ISR[i] == 0)
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continue;
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/* the bootloader may have left it enabled (bad !) */
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openpic2_disable_irq(i+offset);
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sense = (i < OpenPIC_NumInitSenses)? OpenPIC_InitSenses[i]: \
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(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE);
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if (sense & IRQ_SENSE_MASK)
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irq_desc[i+offset].status = IRQ_LEVEL;
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/* Enabled, Priority 8 */
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openpic2_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
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(sense & IRQ_SENSE_MASK));
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/* Processor 0 */
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openpic2_mapirq(i, 1<<0, 0);
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}
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/* Init descriptors */
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for (i = offset; i < NumSources + offset; i++)
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irq_desc[i].handler = &open_pic2;
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/* Initialize the spurious interrupt */
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if (ppc_md.progress) ppc_md.progress("openpic2: spurious",0x3bd);
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openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+offset);
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openpic2_disable_8259_pass_through();
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openpic2_set_priority(0);
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if (ppc_md.progress) ppc_md.progress("openpic2: exit",0x222);
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}
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#ifdef notused
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static void openpic2_enable_8259_pass_through(void)
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{
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openpic2_clearfield(&OpenPIC2->Global.Global_Configuration0,
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OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
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}
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#endif /* notused */
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/* This can't be __init, it is used in openpic_sleep_restore_intrs */
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static void openpic2_disable_8259_pass_through(void)
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{
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openpic2_setfield(&OpenPIC2->Global.Global_Configuration0,
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OPENPIC_CONFIG_8259_PASSTHROUGH_DISABLE);
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}
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/*
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* Find out the current interrupt
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*/
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u_int openpic2_irq(void)
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{
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u_int vec;
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DECL_THIS_CPU;
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CHECK_THIS_CPU;
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vec = openpic2_readfield(&OpenPIC2->THIS_CPU.Interrupt_Acknowledge,
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OPENPIC_VECTOR_MASK);
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return vec;
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}
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void openpic2_eoi(void)
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{
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DECL_THIS_CPU;
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CHECK_THIS_CPU;
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openpic2_write(&OpenPIC2->THIS_CPU.EOI, 0);
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/* Handle PCI write posting */
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(void)openpic2_read(&OpenPIC2->THIS_CPU.EOI);
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}
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#ifdef notused
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static u_int openpic2_get_priority(void)
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{
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DECL_THIS_CPU;
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CHECK_THIS_CPU;
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return openpic2_readfield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
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OPENPIC_CURRENT_TASK_PRIORITY_MASK);
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}
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#endif /* notused */
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static void __init openpic2_set_priority(u_int pri)
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{
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DECL_THIS_CPU;
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CHECK_THIS_CPU;
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check_arg_pri(pri);
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openpic2_writefield(&OpenPIC2->THIS_CPU.Current_Task_Priority,
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OPENPIC_CURRENT_TASK_PRIORITY_MASK, pri);
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}
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/*
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* Get/set the spurious vector
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*/
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#ifdef notused
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static u_int openpic2_get_spurious(void)
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{
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return openpic2_readfield(&OpenPIC2->Global.Spurious_Vector,
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OPENPIC_VECTOR_MASK);
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}
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#endif /* notused */
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/* This can't be __init, it is used in openpic_sleep_restore_intrs */
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static void openpic2_set_spurious(u_int vec)
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{
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check_arg_vec(vec);
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openpic2_writefield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK,
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vec);
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}
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static DEFINE_SPINLOCK(openpic2_setup_lock);
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/*
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* Initialize a timer interrupt (and disable it)
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*
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* timer: OpenPIC timer number
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* pri: interrupt source priority
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* vec: the vector it will produce
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*/
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static void __init openpic2_inittimer(u_int timer, u_int pri, u_int vec)
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{
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check_arg_timer(timer);
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check_arg_pri(pri);
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check_arg_vec(vec);
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openpic2_safe_writefield(&OpenPIC2->Global.Timer[timer].Vector_Priority,
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OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK,
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(pri << OPENPIC_PRIORITY_SHIFT) | vec);
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}
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/*
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* Map a timer interrupt to one or more CPUs
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*/
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static void __init openpic2_maptimer(u_int timer, u_int cpumask)
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{
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check_arg_timer(timer);
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openpic2_write(&OpenPIC2->Global.Timer[timer].Destination,
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cpumask);
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}
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/*
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* Initalize the interrupt source which will generate an NMI.
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* This raises the interrupt's priority from 8 to 9.
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*
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* irq: The logical IRQ which generates an NMI.
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*/
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void __init
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openpic2_init_nmi_irq(u_int irq)
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{
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check_arg_irq(irq);
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openpic2_safe_writefield(&ISR[irq - open_pic2_irq_offset]->Vector_Priority,
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OPENPIC_PRIORITY_MASK,
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9 << OPENPIC_PRIORITY_SHIFT);
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}
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/*
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*
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* All functions below take an offset'ed irq argument
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*
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*/
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/*
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* Enable/disable an external interrupt source
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*
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* Externally called, irq is an offseted system-wide interrupt number
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*/
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static void openpic2_enable_irq(u_int irq)
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{
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volatile u_int *vpp;
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check_arg_irq(irq);
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vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
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openpic2_clearfield(vpp, OPENPIC_MASK);
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/* make sure mask gets to controller before we return to user */
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do {
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mb(); /* sync is probably useless here */
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} while (openpic2_readfield(vpp, OPENPIC_MASK));
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}
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static void openpic2_disable_irq(u_int irq)
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{
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volatile u_int *vpp;
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u32 vp;
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check_arg_irq(irq);
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vpp = &ISR[irq - open_pic2_irq_offset]->Vector_Priority;
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openpic2_setfield(vpp, OPENPIC_MASK);
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/* make sure mask gets to controller before we return to user */
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do {
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mb(); /* sync is probably useless here */
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vp = openpic2_readfield(vpp, OPENPIC_MASK | OPENPIC_ACTIVITY);
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} while((vp & OPENPIC_ACTIVITY) && !(vp & OPENPIC_MASK));
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}
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/*
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* Initialize an interrupt source (and disable it!)
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*
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* irq: OpenPIC interrupt number
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* pri: interrupt source priority
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* vec: the vector it will produce
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* pol: polarity (1 for positive, 0 for negative)
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* sense: 1 for level, 0 for edge
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*/
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static void __init
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openpic2_initirq(u_int irq, u_int pri, u_int vec, int pol, int sense)
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{
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openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
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OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
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OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK,
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(pri << OPENPIC_PRIORITY_SHIFT) | vec |
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(pol ? OPENPIC_POLARITY_POSITIVE :
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OPENPIC_POLARITY_NEGATIVE) |
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(sense ? OPENPIC_SENSE_LEVEL : OPENPIC_SENSE_EDGE));
|
|
}
|
|
|
|
/*
|
|
* Map an interrupt source to one or more CPUs
|
|
*/
|
|
static void openpic2_mapirq(u_int irq, u_int physmask, u_int keepmask)
|
|
{
|
|
if (ISR[irq] == 0)
|
|
return;
|
|
if (keepmask != 0)
|
|
physmask |= openpic2_read(&ISR[irq]->Destination) & keepmask;
|
|
openpic2_write(&ISR[irq]->Destination, physmask);
|
|
}
|
|
|
|
#ifdef notused
|
|
/*
|
|
* Set the sense for an interrupt source (and disable it!)
|
|
*
|
|
* sense: 1 for level, 0 for edge
|
|
*/
|
|
static void openpic2_set_sense(u_int irq, int sense)
|
|
{
|
|
if (ISR[irq] != 0)
|
|
openpic2_safe_writefield(&ISR[irq]->Vector_Priority,
|
|
OPENPIC_SENSE_LEVEL,
|
|
(sense ? OPENPIC_SENSE_LEVEL : 0));
|
|
}
|
|
#endif /* notused */
|
|
|
|
/* No spinlocks, should not be necessary with the OpenPIC
|
|
* (1 register = 1 interrupt and we have the desc lock).
|
|
*/
|
|
static void openpic2_ack_irq(unsigned int irq_nr)
|
|
{
|
|
openpic2_disable_irq(irq_nr);
|
|
openpic2_eoi();
|
|
}
|
|
|
|
static void openpic2_end_irq(unsigned int irq_nr)
|
|
{
|
|
if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
|
|
openpic2_enable_irq(irq_nr);
|
|
}
|
|
|
|
int
|
|
openpic2_get_irq(struct pt_regs *regs)
|
|
{
|
|
int irq = openpic2_irq();
|
|
|
|
if (irq == (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset))
|
|
irq = -1;
|
|
return irq;
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
/*
|
|
* We implement the IRQ controller as a sysdev and put it
|
|
* to sleep at powerdown stage (the callback is named suspend,
|
|
* but it's old semantics, for the Device Model, it's really
|
|
* powerdown). The possible problem is that another sysdev that
|
|
* happens to be suspend after this one will have interrupts off,
|
|
* that may be an issue... For now, this isn't an issue on pmac
|
|
* though...
|
|
*/
|
|
|
|
static u32 save_ipi_vp[OPENPIC_NUM_IPI];
|
|
static u32 save_irq_src_vp[OPENPIC_MAX_SOURCES];
|
|
static u32 save_irq_src_dest[OPENPIC_MAX_SOURCES];
|
|
static u32 save_cpu_task_pri[OPENPIC_MAX_PROCESSORS];
|
|
static int openpic_suspend_count;
|
|
|
|
static void openpic2_cached_enable_irq(u_int irq)
|
|
{
|
|
check_arg_irq(irq);
|
|
save_irq_src_vp[irq - open_pic2_irq_offset] &= ~OPENPIC_MASK;
|
|
}
|
|
|
|
static void openpic2_cached_disable_irq(u_int irq)
|
|
{
|
|
check_arg_irq(irq);
|
|
save_irq_src_vp[irq - open_pic2_irq_offset] |= OPENPIC_MASK;
|
|
}
|
|
|
|
/* WARNING: Can be called directly by the cpufreq code with NULL parameter,
|
|
* we need something better to deal with that... Maybe switch to S1 for
|
|
* cpufreq changes
|
|
*/
|
|
int openpic2_suspend(struct sys_device *sysdev, u32 state)
|
|
{
|
|
int i;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&openpic2_setup_lock, flags);
|
|
|
|
if (openpic_suspend_count++ > 0) {
|
|
spin_unlock_irqrestore(&openpic2_setup_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
open_pic2.enable = openpic2_cached_enable_irq;
|
|
open_pic2.disable = openpic2_cached_disable_irq;
|
|
|
|
for (i=0; i<NumProcessors; i++) {
|
|
save_cpu_task_pri[i] = openpic2_read(&OpenPIC2->Processor[i].Current_Task_Priority);
|
|
openpic2_writefield(&OpenPIC2->Processor[i].Current_Task_Priority,
|
|
OPENPIC_CURRENT_TASK_PRIORITY_MASK, 0xf);
|
|
}
|
|
|
|
for (i=0; i<OPENPIC_NUM_IPI; i++)
|
|
save_ipi_vp[i] = openpic2_read(&OpenPIC2->Global.IPI_Vector_Priority(i));
|
|
for (i=0; i<NumSources; i++) {
|
|
if (ISR[i] == 0)
|
|
continue;
|
|
save_irq_src_vp[i] = openpic2_read(&ISR[i]->Vector_Priority) & ~OPENPIC_ACTIVITY;
|
|
save_irq_src_dest[i] = openpic2_read(&ISR[i]->Destination);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&openpic2_setup_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* WARNING: Can be called directly by the cpufreq code with NULL parameter,
|
|
* we need something better to deal with that... Maybe switch to S1 for
|
|
* cpufreq changes
|
|
*/
|
|
int openpic2_resume(struct sys_device *sysdev)
|
|
{
|
|
int i;
|
|
unsigned long flags;
|
|
u32 vppmask = OPENPIC_PRIORITY_MASK | OPENPIC_VECTOR_MASK |
|
|
OPENPIC_SENSE_MASK | OPENPIC_POLARITY_MASK |
|
|
OPENPIC_MASK;
|
|
|
|
spin_lock_irqsave(&openpic2_setup_lock, flags);
|
|
|
|
if ((--openpic_suspend_count) > 0) {
|
|
spin_unlock_irqrestore(&openpic2_setup_lock, flags);
|
|
return 0;
|
|
}
|
|
|
|
openpic2_reset();
|
|
|
|
/* OpenPIC sometimes seem to need some time to be fully back up... */
|
|
do {
|
|
openpic2_set_spurious(OPENPIC2_VEC_SPURIOUS+open_pic2_irq_offset);
|
|
} while(openpic2_readfield(&OpenPIC2->Global.Spurious_Vector, OPENPIC_VECTOR_MASK)
|
|
!= (OPENPIC2_VEC_SPURIOUS + open_pic2_irq_offset));
|
|
|
|
openpic2_disable_8259_pass_through();
|
|
|
|
for (i=0; i<OPENPIC_NUM_IPI; i++)
|
|
openpic2_write(&OpenPIC2->Global.IPI_Vector_Priority(i),
|
|
save_ipi_vp[i]);
|
|
for (i=0; i<NumSources; i++) {
|
|
if (ISR[i] == 0)
|
|
continue;
|
|
openpic2_write(&ISR[i]->Destination, save_irq_src_dest[i]);
|
|
openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
|
|
/* make sure mask gets to controller before we return to user */
|
|
do {
|
|
openpic2_write(&ISR[i]->Vector_Priority, save_irq_src_vp[i]);
|
|
} while (openpic2_readfield(&ISR[i]->Vector_Priority, vppmask)
|
|
!= (save_irq_src_vp[i] & vppmask));
|
|
}
|
|
for (i=0; i<NumProcessors; i++)
|
|
openpic2_write(&OpenPIC2->Processor[i].Current_Task_Priority,
|
|
save_cpu_task_pri[i]);
|
|
|
|
open_pic2.enable = openpic2_enable_irq;
|
|
open_pic2.disable = openpic2_disable_irq;
|
|
|
|
spin_unlock_irqrestore(&openpic2_setup_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
/* HACK ALERT */
|
|
static struct sysdev_class openpic2_sysclass = {
|
|
set_kset_name("openpic2"),
|
|
};
|
|
|
|
static struct sys_device device_openpic2 = {
|
|
.id = 0,
|
|
.cls = &openpic2_sysclass,
|
|
};
|
|
|
|
static struct sysdev_driver driver_openpic2 = {
|
|
#ifdef CONFIG_PM
|
|
.suspend = &openpic2_suspend,
|
|
.resume = &openpic2_resume,
|
|
#endif /* CONFIG_PM */
|
|
};
|
|
|
|
static int __init init_openpic2_sysfs(void)
|
|
{
|
|
int rc;
|
|
|
|
if (!OpenPIC2_Addr)
|
|
return -ENODEV;
|
|
printk(KERN_DEBUG "Registering openpic2 with sysfs...\n");
|
|
rc = sysdev_class_register(&openpic2_sysclass);
|
|
if (rc) {
|
|
printk(KERN_ERR "Failed registering openpic sys class\n");
|
|
return -ENODEV;
|
|
}
|
|
rc = sysdev_register(&device_openpic2);
|
|
if (rc) {
|
|
printk(KERN_ERR "Failed registering openpic sys device\n");
|
|
return -ENODEV;
|
|
}
|
|
rc = sysdev_driver_register(&openpic2_sysclass, &driver_openpic2);
|
|
if (rc) {
|
|
printk(KERN_ERR "Failed registering openpic sys driver\n");
|
|
return -ENODEV;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(init_openpic2_sysfs);
|
|
|