157 lines
3.5 KiB
C
157 lines
3.5 KiB
C
/*
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* tegra_asoc_utils.c - Harmony machine ASoC driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010 - NVIDIA, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include "tegra_asoc_utils.h"
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int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
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int mclk)
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{
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int new_baseclock;
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bool clk_change;
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int err;
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switch (srate) {
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case 11025:
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case 22050:
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case 44100:
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case 88200:
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new_baseclock = 56448000;
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break;
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case 8000:
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case 16000:
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case 32000:
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case 48000:
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case 64000:
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case 96000:
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new_baseclock = 73728000;
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break;
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default:
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return -EINVAL;
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}
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clk_change = ((new_baseclock != data->set_baseclock) ||
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(mclk != data->set_mclk));
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if (!clk_change)
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return 0;
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data->set_baseclock = 0;
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data->set_mclk = 0;
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clk_disable(data->clk_cdev1);
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clk_disable(data->clk_pll_a_out0);
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clk_disable(data->clk_pll_a);
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err = clk_set_rate(data->clk_pll_a, new_baseclock);
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if (err) {
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dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
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return err;
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}
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err = clk_set_rate(data->clk_pll_a_out0, mclk);
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if (err) {
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dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
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return err;
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}
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/* Don't set cdev1 rate; its locked to pll_a_out0 */
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err = clk_enable(data->clk_pll_a);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a: %d\n", err);
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return err;
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}
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err = clk_enable(data->clk_pll_a_out0);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
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return err;
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}
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err = clk_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", err);
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return err;
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}
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data->set_baseclock = new_baseclock;
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data->set_mclk = mclk;
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return 0;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_set_rate);
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int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
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struct device *dev)
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{
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int ret;
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data->dev = dev;
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data->clk_pll_a = clk_get_sys(NULL, "pll_a");
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if (IS_ERR(data->clk_pll_a)) {
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dev_err(data->dev, "Can't retrieve clk pll_a\n");
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ret = PTR_ERR(data->clk_pll_a);
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goto err;
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}
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data->clk_pll_a_out0 = clk_get_sys(NULL, "pll_a_out0");
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if (IS_ERR(data->clk_pll_a_out0)) {
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dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
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ret = PTR_ERR(data->clk_pll_a_out0);
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goto err_put_pll_a;
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}
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data->clk_cdev1 = clk_get_sys(NULL, "cdev1");
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if (IS_ERR(data->clk_cdev1)) {
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dev_err(data->dev, "Can't retrieve clk cdev1\n");
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ret = PTR_ERR(data->clk_cdev1);
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goto err_put_pll_a_out0;
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}
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return 0;
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err_put_pll_a_out0:
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clk_put(data->clk_pll_a_out0);
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err_put_pll_a:
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clk_put(data->clk_pll_a);
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err:
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return ret;
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_init);
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void tegra_asoc_utils_fini(struct tegra_asoc_utils_data *data)
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{
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clk_put(data->clk_cdev1);
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clk_put(data->clk_pll_a_out0);
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clk_put(data->clk_pll_a);
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}
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EXPORT_SYMBOL_GPL(tegra_asoc_utils_fini);
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MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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MODULE_DESCRIPTION("Tegra ASoC utility code");
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MODULE_LICENSE("GPL");
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