90 lines
3.6 KiB
C
90 lines
3.6 KiB
C
#ifndef _MACH_PORTMUX_H_
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#define _MACH_PORTMUX_H_
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#define MAX_RESOURCES MAX_BLACKFIN_GPIOS
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#define P_PPI0_CLK (P_DONTCARE)
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#define P_PPI0_FS1 (P_DONTCARE)
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#define P_PPI0_FS2 (P_DONTCARE)
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#define P_PPI0_FS3 (P_DONTCARE)
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#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
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#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
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#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
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#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
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#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
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#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
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#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
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#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
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#define P_PPI0_D0 (P_DONTCARE)
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#define P_PPI0_D1 (P_DONTCARE)
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#define P_PPI0_D2 (P_DONTCARE)
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#define P_PPI0_D3 (P_DONTCARE)
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#define P_PPI0_D4 (P_DONTCARE)
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#define P_PPI0_D5 (P_DONTCARE)
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#define P_PPI0_D6 (P_DONTCARE)
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#define P_PPI0_D7 (P_DONTCARE)
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#define P_PPI1_CLK (P_DONTCARE)
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#define P_PPI1_FS1 (P_DONTCARE)
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#define P_PPI1_FS2 (P_DONTCARE)
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#define P_PPI1_FS3 (P_DONTCARE)
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#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
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#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
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#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
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#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
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#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
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#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
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#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
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#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
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#define P_PPI1_D0 (P_DONTCARE)
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#define P_PPI1_D1 (P_DONTCARE)
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#define P_PPI1_D2 (P_DONTCARE)
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#define P_PPI1_D3 (P_DONTCARE)
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#define P_PPI1_D4 (P_DONTCARE)
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#define P_PPI1_D5 (P_DONTCARE)
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#define P_PPI1_D6 (P_DONTCARE)
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#define P_PPI1_D7 (P_DONTCARE)
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#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
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#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
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#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
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#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
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#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
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#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
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#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
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#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
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#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
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#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
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#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
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#define P_SPORT1_DRPRI (P_DONTCARE)
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#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
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#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
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#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
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#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
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#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
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#define P_SPORT0_DRPRI (P_DONTCARE)
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#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
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#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
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#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
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#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
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#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
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#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
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#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
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#define P_TMR11 (P_DONTCARE)
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#define P_TMR10 (P_DONTCARE)
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#define P_TMR9 (P_DONTCARE)
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#define P_TMR8 (P_DONTCARE)
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#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
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#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
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#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
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#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
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#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
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#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
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#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
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#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
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#define P_SPI0_MOSI (P_DONTCARE)
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#define P_SPI0_MISO (P_DONTCARE)
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#define P_SPI0_SCK (P_DONTCARE)
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#endif /* _MACH_PORTMUX_H_ */
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