332 lines
8.1 KiB
C
332 lines
8.1 KiB
C
/*
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* omap-pm-noop.c - OMAP power management interface - dummy version
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*
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* This code implements the OMAP power management interface to
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* drivers, CPUIdle, CPUFreq, and DSP Bridge. It is strictly for
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* debug/demonstration use, as it does nothing but printk() whenever a
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* function is called (when DEBUG is defined, below)
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*
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* Copyright (C) 2008-2009 Texas Instruments, Inc.
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* Copyright (C) 2008-2009 Nokia Corporation
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* Paul Walmsley
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*
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* Interface developed by (in alphabetical order):
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* Karthik Dasu, Tony Lindgren, Rajendra Nayak, Sakari Poussa, Veeramanikandan
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* Raju, Anand Sawant, Igor Stoppa, Paul Walmsley, Richard Woodruff
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*/
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#undef DEBUG
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/device.h>
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/* Interface documentation is in mach/omap-pm.h */
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#include <plat/omap-pm.h>
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#include <plat/powerdomain.h>
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struct omap_opp *dsp_opps;
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struct omap_opp *mpu_opps;
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struct omap_opp *l3_opps;
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/*
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* Device-driver-originated constraints (via board-*.c files)
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*/
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int omap_pm_set_max_mpu_wakeup_lat(struct device *dev, long t)
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{
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if (!dev || t < -1) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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};
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if (t == -1)
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pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
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"dev %s\n", dev_name(dev));
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else
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pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
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"dev %s, t = %ld usec\n", dev_name(dev), t);
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/*
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* For current Linux, this needs to map the MPU to a
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* powerdomain, then go through the list of current max lat
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* constraints on the MPU and find the smallest. If
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* the latency constraint has changed, the code should
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* recompute the state to enter for the next powerdomain
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* state.
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*
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* TI CDP code can call constraint_set here.
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*/
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return 0;
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}
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int omap_pm_set_min_bus_tput(struct device *dev, u8 agent_id, unsigned long r)
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{
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if (!dev || (agent_id != OCP_INITIATOR_AGENT &&
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agent_id != OCP_TARGET_AGENT)) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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};
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if (r == 0)
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pr_debug("OMAP PM: remove min bus tput constraint: "
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"dev %s for agent_id %d\n", dev_name(dev), agent_id);
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else
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pr_debug("OMAP PM: add min bus tput constraint: "
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"dev %s for agent_id %d: rate %ld KiB\n",
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dev_name(dev), agent_id, r);
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/*
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* This code should model the interconnect and compute the
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* required clock frequency, convert that to a VDD2 OPP ID, then
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* set the VDD2 OPP appropriately.
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*
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* TI CDP code can call constraint_set here on the VDD2 OPP.
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*/
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return 0;
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}
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int omap_pm_set_max_dev_wakeup_lat(struct device *req_dev, struct device *dev,
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long t)
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{
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if (!req_dev || !dev || t < -1) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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};
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if (t == -1)
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pr_debug("OMAP PM: remove max device latency constraint: "
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"dev %s\n", dev_name(dev));
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else
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pr_debug("OMAP PM: add max device latency constraint: "
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"dev %s, t = %ld usec\n", dev_name(dev), t);
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/*
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* For current Linux, this needs to map the device to a
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* powerdomain, then go through the list of current max lat
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* constraints on that powerdomain and find the smallest. If
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* the latency constraint has changed, the code should
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* recompute the state to enter for the next powerdomain
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* state. Conceivably, this code should also determine
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* whether to actually disable the device clocks or not,
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* depending on how long it takes to re-enable the clocks.
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*
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* TI CDP code can call constraint_set here.
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*/
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return 0;
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}
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int omap_pm_set_max_sdma_lat(struct device *dev, long t)
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{
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if (!dev || t < -1) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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};
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if (t == -1)
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pr_debug("OMAP PM: remove max DMA latency constraint: "
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"dev %s\n", dev_name(dev));
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else
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pr_debug("OMAP PM: add max DMA latency constraint: "
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"dev %s, t = %ld usec\n", dev_name(dev), t);
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/*
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* For current Linux PM QOS params, this code should scan the
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* list of maximum CPU and DMA latencies and select the
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* smallest, then set cpu_dma_latency pm_qos_param
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* accordingly.
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*
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* For future Linux PM QOS params, with separate CPU and DMA
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* latency params, this code should just set the dma_latency param.
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*
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* TI CDP code can call constraint_set here.
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*/
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return 0;
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}
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int omap_pm_set_min_clk_rate(struct device *dev, struct clk *c, long r)
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{
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if (!dev || !c || r < 0) {
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WARN(1, "OMAP PM: %s: invalid parameter(s)", __func__);
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return -EINVAL;
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}
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if (r == 0)
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pr_debug("OMAP PM: remove min clk rate constraint: "
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"dev %s\n", dev_name(dev));
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else
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pr_debug("OMAP PM: add min clk rate constraint: "
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"dev %s, rate = %ld Hz\n", dev_name(dev), r);
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/*
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* Code in a real implementation should keep track of these
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* constraints on the clock, and determine the highest minimum
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* clock rate. It should iterate over each OPP and determine
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* whether the OPP will result in a clock rate that would
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* satisfy this constraint (and any other PM constraint in effect
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* at that time). Once it finds the lowest-voltage OPP that
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* meets those conditions, it should switch to it, or return
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* an error if the code is not capable of doing so.
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*/
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return 0;
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}
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/*
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* DSP Bridge-specific constraints
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*/
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const struct omap_opp *omap_pm_dsp_get_opp_table(void)
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{
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pr_debug("OMAP PM: DSP request for OPP table\n");
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/*
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* Return DSP frequency table here: The final item in the
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* array should have .rate = .opp_id = 0.
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*/
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return NULL;
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}
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void omap_pm_dsp_set_min_opp(u8 opp_id)
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{
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if (opp_id == 0) {
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WARN_ON(1);
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return;
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}
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pr_debug("OMAP PM: DSP requests minimum VDD1 OPP to be %d\n", opp_id);
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/*
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*
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* For l-o dev tree, our VDD1 clk is keyed on OPP ID, so we
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* can just test to see which is higher, the CPU's desired OPP
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* ID or the DSP's desired OPP ID, and use whichever is
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* highest.
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*
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* In CDP12.14+, the VDD1 OPP custom clock that controls the DSP
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* rate is keyed on MPU speed, not the OPP ID. So we need to
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* map the OPP ID to the MPU speed for use with clk_set_rate()
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* if it is higher than the current OPP clock rate.
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*
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*/
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}
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u8 omap_pm_dsp_get_opp(void)
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{
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pr_debug("OMAP PM: DSP requests current DSP OPP ID\n");
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/*
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* For l-o dev tree, call clk_get_rate() on VDD1 OPP clock
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*
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* CDP12.14+:
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* Call clk_get_rate() on the OPP custom clock, map that to an
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* OPP ID using the tables defined in board-*.c/chip-*.c files.
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*/
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return 0;
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}
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/*
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* CPUFreq-originated constraint
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*
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* In the future, this should be handled by custom OPP clocktype
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* functions.
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*/
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struct cpufreq_frequency_table **omap_pm_cpu_get_freq_table(void)
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{
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pr_debug("OMAP PM: CPUFreq request for frequency table\n");
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/*
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* Return CPUFreq frequency table here: loop over
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* all VDD1 clkrates, pull out the mpu_ck frequencies, build
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* table
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*/
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return NULL;
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}
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void omap_pm_cpu_set_freq(unsigned long f)
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{
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if (f == 0) {
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WARN_ON(1);
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return;
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}
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pr_debug("OMAP PM: CPUFreq requests CPU frequency to be set to %lu\n",
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f);
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/*
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* For l-o dev tree, determine whether MPU freq or DSP OPP id
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* freq is higher. Find the OPP ID corresponding to the
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* higher frequency. Call clk_round_rate() and clk_set_rate()
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* on the OPP custom clock.
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*
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* CDP should just be able to set the VDD1 OPP clock rate here.
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*/
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}
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unsigned long omap_pm_cpu_get_freq(void)
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{
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pr_debug("OMAP PM: CPUFreq requests current CPU frequency\n");
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/*
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* Call clk_get_rate() on the mpu_ck.
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*/
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return 0;
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}
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/*
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* Device context loss tracking
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*/
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int omap_pm_get_dev_context_loss_count(struct device *dev)
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{
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if (!dev) {
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WARN_ON(1);
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return -EINVAL;
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};
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pr_debug("OMAP PM: returning context loss count for dev %s\n",
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dev_name(dev));
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/*
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* Map the device to the powerdomain. Return the powerdomain
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* off counter.
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*/
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return 0;
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}
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/* Should be called before clk framework init */
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int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
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struct omap_opp *dsp_opp_table,
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struct omap_opp *l3_opp_table)
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{
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mpu_opps = mpu_opp_table;
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dsp_opps = dsp_opp_table;
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l3_opps = l3_opp_table;
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return 0;
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}
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/* Must be called after clock framework is initialized */
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int __init omap_pm_if_init(void)
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{
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return 0;
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}
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void omap_pm_if_exit(void)
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{
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/* Deallocate CPUFreq frequency table here */
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}
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