57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/*
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* Copyright (C) 2009-2010 Pengutronix
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* Sascha Hauer <s.hauer@pengutronix.de>
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* Juergen Beisert <j.beisert@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify it under
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* the terms of the GNU General Public License version 2 as published by the
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* Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <mach/hardware.h>
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static int mxc_init_l2x0(void)
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{
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void __iomem *l2x0_base;
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void __iomem *clkctl_base;
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if (!cpu_is_mx31() && !cpu_is_mx35())
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return 0;
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/*
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* First of all, we must repair broken chip settings. There are some
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* i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
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* misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
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* Workaraound is to setup the correct register setting prior enabling the
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* L2 cache. This should not hurt already working CPUs, as they are using the
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* same value.
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*/
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#define L2_MEM_VAL 0x10
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clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
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if (clkctl_base != NULL) {
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writel(0x00000515, clkctl_base + L2_MEM_VAL);
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iounmap(clkctl_base);
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} else {
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pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
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}
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l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
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if (IS_ERR(l2x0_base)) {
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printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
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PTR_ERR(l2x0_base));
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return 0;
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}
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l2x0_init(l2x0_base, 0x00030024, 0x00000000);
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return 0;
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}
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arch_initcall(mxc_init_l2x0);
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