185 lines
5.6 KiB
C
185 lines
5.6 KiB
C
/**********************************************************************
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* Author: Cavium, Inc.
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*
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* Contact: support@cavium.com
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* Please include "LiquidIO" in the subject.
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*
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* Copyright (c) 2003-2016 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more details.
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***********************************************************************/
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#include <linux/pci.h>
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#include <linux/netdevice.h>
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#include "liquidio_common.h"
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#include "octeon_droq.h"
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#include "octeon_iq.h"
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#include "response_manager.h"
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#include "octeon_device.h"
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#include "octeon_main.h"
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#include "cn66xx_regs.h"
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#include "cn66xx_device.h"
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#include "cn68xx_device.h"
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#include "cn68xx_regs.h"
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static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct)
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{
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u32 i;
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u32 fifo_sizes[6] = { 3, 3, 1, 1, 1, 8 };
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lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL);
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dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n",
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lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL));
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for (i = 0; i < 6; i++) {
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/* Prevent service of instruction queue for all DMA engines
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* Engine 5 will remain 0. Engines 0 - 4 will be setup by
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* core.
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*/
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lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i));
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lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i));
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dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i,
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lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i)));
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}
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/* DPI_SLI_PRT_CFG has MPS and MRRS settings that will be set
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* separately.
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*/
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lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL);
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dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n",
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lio_pci_readq(oct, CN6XXX_DPI_CTL));
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}
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static int lio_cn68xx_soft_reset(struct octeon_device *oct)
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{
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lio_cn6xxx_soft_reset(oct);
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lio_cn68xx_set_dpi_regs(oct);
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return 0;
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}
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static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct)
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{
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struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
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u64 pktctl, tx_pipe, max_oqs;
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pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL);
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/* 68XX specific */
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max_oqs = CFG_GET_OQ_MAX_Q(CHIP_CONF(oct, cn6xxx));
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tx_pipe = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE);
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tx_pipe &= 0xffffffffff00ffffULL; /* clear out NUMP field */
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tx_pipe |= max_oqs << 16; /* put max_oqs in NUMP field */
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octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe);
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if (CFG_GET_IS_SLI_BP_ON(cn68xx->conf))
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pktctl |= 0xF;
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else
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/* Disable per-port backpressure. */
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pktctl &= ~0xF;
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octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl);
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}
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static int lio_cn68xx_setup_device_regs(struct octeon_device *oct)
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{
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lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT);
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lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B);
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lio_cn6xxx_enable_error_reporting(oct);
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lio_cn6xxx_setup_global_input_regs(oct);
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lio_cn68xx_setup_pkt_ctl_regs(oct);
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lio_cn6xxx_setup_global_output_regs(oct);
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/* Default error timeout value should be 0x200000 to avoid host hang
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* when reads invalid register
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*/
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octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL);
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return 0;
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}
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static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct)
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{
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u32 val = 0;
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/* Set M_VEND1_DRP and M_VEND0_DRP bits */
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pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val);
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val |= 0x3;
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pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val);
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}
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static int lio_is_210nv(struct octeon_device *oct)
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{
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u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG);
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return ((mio_qlm4_cfg & CN6XXX_MIO_QLM_CFG_MASK) == 0);
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}
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int lio_setup_cn68xx_octeon_device(struct octeon_device *oct)
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{
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struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
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u16 card_type = LIO_410NV;
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if (octeon_map_pci_barx(oct, 0, 0))
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return 1;
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if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {
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dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n",
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__func__);
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octeon_unmap_pci_barx(oct, 0);
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return 1;
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}
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spin_lock_init(&cn68xx->lock_for_droq_int_enb_reg);
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oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs;
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oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs;
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oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs;
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oct->fn_list.soft_reset = lio_cn68xx_soft_reset;
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oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs;
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oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index;
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oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup;
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oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write;
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oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read;
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oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt;
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oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt;
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oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues;
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oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues;
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lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list);
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/* Determine variant of card */
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if (lio_is_210nv(oct))
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card_type = LIO_210NV;
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cn68xx->conf = (struct octeon_config *)
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oct_get_config_info(oct, card_type);
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if (!cn68xx->conf) {
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dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n",
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__func__,
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(card_type == LIO_410NV) ? LIO_410NV_NAME :
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LIO_210NV_NAME);
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octeon_unmap_pci_barx(oct, 0);
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octeon_unmap_pci_barx(oct, 1);
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return 1;
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}
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oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct);
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lio_cn68xx_vendor_message_fix(oct);
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return 0;
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}
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EXPORT_SYMBOL_GPL(lio_setup_cn68xx_octeon_device);
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