438 lines
11 KiB
C
438 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* cdns3-imx.c - NXP i.MX specific Glue layer for Cadence USB Controller
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*
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* Copyright (C) 2019 NXP
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*/
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/of_platform.h>
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#include <linux/iopoll.h>
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#include <linux/pm_runtime.h>
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#include "core.h"
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#define USB3_CORE_CTRL1 0x00
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#define USB3_CORE_CTRL2 0x04
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#define USB3_INT_REG 0x08
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#define USB3_CORE_STATUS 0x0c
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#define XHCI_DEBUG_LINK_ST 0x10
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#define XHCI_DEBUG_BUS 0x14
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#define USB3_SSPHY_CTRL1 0x40
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#define USB3_SSPHY_CTRL2 0x44
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#define USB3_SSPHY_STATUS 0x4c
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#define USB2_PHY_CTRL1 0x50
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#define USB2_PHY_CTRL2 0x54
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#define USB2_PHY_STATUS 0x5c
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/* Register bits definition */
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/* USB3_CORE_CTRL1 */
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#define SW_RESET_MASK GENMASK(31, 26)
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#define PWR_SW_RESET BIT(31)
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#define APB_SW_RESET BIT(30)
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#define AXI_SW_RESET BIT(29)
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#define RW_SW_RESET BIT(28)
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#define PHY_SW_RESET BIT(27)
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#define PHYAHB_SW_RESET BIT(26)
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#define ALL_SW_RESET (PWR_SW_RESET | APB_SW_RESET | AXI_SW_RESET | \
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RW_SW_RESET | PHY_SW_RESET | PHYAHB_SW_RESET)
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#define OC_DISABLE BIT(9)
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#define MDCTRL_CLK_SEL BIT(7)
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#define MODE_STRAP_MASK (0x7)
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#define DEV_MODE (1 << 2)
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#define HOST_MODE (1 << 1)
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#define OTG_MODE (1 << 0)
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/* USB3_INT_REG */
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#define CLK_125_REQ BIT(29)
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#define LPM_CLK_REQ BIT(28)
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#define DEVU3_WAEKUP_EN BIT(14)
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#define OTG_WAKEUP_EN BIT(12)
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#define DEV_INT_EN (3 << 8) /* DEV INT b9:8 */
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#define HOST_INT1_EN (1 << 0) /* HOST INT b7:0 */
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/* USB3_CORE_STATUS */
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#define MDCTRL_CLK_STATUS BIT(15)
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#define DEV_POWER_ON_READY BIT(13)
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#define HOST_POWER_ON_READY BIT(12)
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/* USB3_SSPHY_STATUS */
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#define CLK_VALID_MASK (0x3f << 26)
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#define CLK_VALID_COMPARE_BITS (0xf << 28)
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#define PHY_REFCLK_REQ (1 << 0)
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/* OTG registers definition */
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#define OTGSTS 0x4
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/* OTGSTS */
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#define OTG_NRDY BIT(11)
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/* xHCI registers definition */
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#define XECP_PM_PMCSR 0x8018
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#define XECP_AUX_CTRL_REG1 0x8120
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/* Register bits definition */
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/* XECP_AUX_CTRL_REG1 */
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#define CFG_RXDET_P3_EN BIT(15)
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/* XECP_PM_PMCSR */
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#define PS_MASK GENMASK(1, 0)
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#define PS_D0 0
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#define PS_D1 1
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struct cdns_imx {
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struct device *dev;
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void __iomem *noncore;
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struct clk_bulk_data *clks;
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int num_clks;
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struct platform_device *cdns3_pdev;
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};
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static inline u32 cdns_imx_readl(struct cdns_imx *data, u32 offset)
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{
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return readl(data->noncore + offset);
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}
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static inline void cdns_imx_writel(struct cdns_imx *data, u32 offset, u32 value)
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{
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writel(value, data->noncore + offset);
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}
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static const struct clk_bulk_data imx_cdns3_core_clks[] = {
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{ .id = "lpm" },
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{ .id = "bus" },
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{ .id = "aclk" },
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{ .id = "ipg" },
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{ .id = "core" },
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};
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static int cdns_imx_noncore_init(struct cdns_imx *data)
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{
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u32 value;
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int ret;
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struct device *dev = data->dev;
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cdns_imx_writel(data, USB3_SSPHY_STATUS, CLK_VALID_MASK);
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udelay(1);
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ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value,
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(value & CLK_VALID_COMPARE_BITS) == CLK_VALID_COMPARE_BITS,
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10, 100000);
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if (ret) {
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dev_err(dev, "wait clkvld timeout\n");
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return ret;
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}
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value |= ALL_SW_RESET;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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udelay(1);
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value = (value & ~MODE_STRAP_MASK) | OTG_MODE | OC_DISABLE;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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value = cdns_imx_readl(data, USB3_INT_REG);
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value |= HOST_INT1_EN | DEV_INT_EN;
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cdns_imx_writel(data, USB3_INT_REG, value);
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value &= ~ALL_SW_RESET;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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return ret;
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}
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static int cdns_imx_platform_suspend(struct device *dev,
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bool suspend, bool wakeup);
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static struct cdns3_platform_data cdns_imx_pdata = {
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.platform_suspend = cdns_imx_platform_suspend,
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.quirks = CDNS3_DEFAULT_PM_RUNTIME_ALLOW,
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};
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static const struct of_dev_auxdata cdns_imx_auxdata[] = {
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{
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.compatible = "cdns,usb3",
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.platform_data = &cdns_imx_pdata,
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},
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{},
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};
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static int cdns_imx_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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struct cdns_imx *data;
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int ret;
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if (!node)
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return -ENODEV;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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platform_set_drvdata(pdev, data);
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data->dev = dev;
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data->noncore = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(data->noncore)) {
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dev_err(dev, "can't map IOMEM resource\n");
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return PTR_ERR(data->noncore);
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}
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data->num_clks = ARRAY_SIZE(imx_cdns3_core_clks);
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data->clks = devm_kmemdup(dev, imx_cdns3_core_clks,
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sizeof(imx_cdns3_core_clks), GFP_KERNEL);
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if (!data->clks)
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return -ENOMEM;
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ret = devm_clk_bulk_get(dev, data->num_clks, data->clks);
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if (ret)
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return ret;
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ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
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if (ret)
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return ret;
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ret = cdns_imx_noncore_init(data);
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if (ret)
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goto err;
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ret = of_platform_populate(node, NULL, cdns_imx_auxdata, dev);
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if (ret) {
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dev_err(dev, "failed to create children: %d\n", ret);
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goto err;
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}
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device_set_wakeup_capable(dev, true);
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pm_runtime_set_active(dev);
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pm_runtime_enable(dev);
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return ret;
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err:
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clk_bulk_disable_unprepare(data->num_clks, data->clks);
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return ret;
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}
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static void cdns_imx_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct cdns_imx *data = dev_get_drvdata(dev);
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pm_runtime_get_sync(dev);
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of_platform_depopulate(dev);
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clk_bulk_disable_unprepare(data->num_clks, data->clks);
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pm_runtime_disable(dev);
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pm_runtime_put_noidle(dev);
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platform_set_drvdata(pdev, NULL);
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}
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#ifdef CONFIG_PM
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static void cdns3_set_wakeup(struct cdns_imx *data, bool enable)
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{
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u32 value;
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value = cdns_imx_readl(data, USB3_INT_REG);
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if (enable)
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value |= OTG_WAKEUP_EN | DEVU3_WAEKUP_EN;
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else
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value &= ~(OTG_WAKEUP_EN | DEVU3_WAEKUP_EN);
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cdns_imx_writel(data, USB3_INT_REG, value);
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}
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static int cdns_imx_platform_suspend(struct device *dev,
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bool suspend, bool wakeup)
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{
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struct cdns *cdns = dev_get_drvdata(dev);
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struct device *parent = dev->parent;
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struct cdns_imx *data = dev_get_drvdata(parent);
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void __iomem *otg_regs = (void __iomem *)(cdns->otg_regs);
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void __iomem *xhci_regs = cdns->xhci_regs;
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u32 value;
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int ret = 0;
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if (cdns->role != USB_ROLE_HOST)
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return 0;
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if (suspend) {
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/* SW request low power when all usb ports allow to it ??? */
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value = readl(xhci_regs + XECP_PM_PMCSR);
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value &= ~PS_MASK;
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value |= PS_D1;
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writel(value, xhci_regs + XECP_PM_PMCSR);
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/* mdctrl_clk_sel */
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value |= MDCTRL_CLK_SEL;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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/* wait for mdctrl_clk_status */
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value = cdns_imx_readl(data, USB3_CORE_STATUS);
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ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value,
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(value & MDCTRL_CLK_STATUS) == MDCTRL_CLK_STATUS,
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10, 100000);
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if (ret)
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dev_warn(parent, "wait mdctrl_clk_status timeout\n");
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/* wait lpm_clk_req to be 0 */
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value = cdns_imx_readl(data, USB3_INT_REG);
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ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value,
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(value & LPM_CLK_REQ) != LPM_CLK_REQ,
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10, 100000);
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if (ret)
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dev_warn(parent, "wait lpm_clk_req timeout\n");
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/* wait phy_refclk_req to be 0 */
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value = cdns_imx_readl(data, USB3_SSPHY_STATUS);
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ret = readl_poll_timeout(data->noncore + USB3_SSPHY_STATUS, value,
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(value & PHY_REFCLK_REQ) != PHY_REFCLK_REQ,
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10, 100000);
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if (ret)
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dev_warn(parent, "wait phy_refclk_req timeout\n");
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cdns3_set_wakeup(data, wakeup);
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} else {
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cdns3_set_wakeup(data, false);
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/* SW request D0 */
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value = readl(xhci_regs + XECP_PM_PMCSR);
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value &= ~PS_MASK;
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value |= PS_D0;
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writel(value, xhci_regs + XECP_PM_PMCSR);
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/* clr CFG_RXDET_P3_EN */
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value = readl(xhci_regs + XECP_AUX_CTRL_REG1);
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value &= ~CFG_RXDET_P3_EN;
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writel(value, xhci_regs + XECP_AUX_CTRL_REG1);
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/* clear mdctrl_clk_sel */
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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value &= ~MDCTRL_CLK_SEL;
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cdns_imx_writel(data, USB3_CORE_CTRL1, value);
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/* wait CLK_125_REQ to be 1 */
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value = cdns_imx_readl(data, USB3_INT_REG);
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ret = readl_poll_timeout(data->noncore + USB3_INT_REG, value,
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(value & CLK_125_REQ) == CLK_125_REQ,
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10, 100000);
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if (ret)
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dev_warn(parent, "wait CLK_125_REQ timeout\n");
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/* wait for mdctrl_clk_status is cleared */
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value = cdns_imx_readl(data, USB3_CORE_STATUS);
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ret = readl_poll_timeout(data->noncore + USB3_CORE_STATUS, value,
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(value & MDCTRL_CLK_STATUS) != MDCTRL_CLK_STATUS,
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10, 100000);
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if (ret)
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dev_warn(parent, "wait mdctrl_clk_status cleared timeout\n");
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/* Wait until OTG_NRDY is 0 */
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value = readl(otg_regs + OTGSTS);
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ret = readl_poll_timeout(otg_regs + OTGSTS, value,
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(value & OTG_NRDY) != OTG_NRDY,
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10, 100000);
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if (ret)
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dev_warn(parent, "wait OTG ready timeout\n");
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}
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return ret;
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}
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static int cdns_imx_resume(struct device *dev)
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{
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struct cdns_imx *data = dev_get_drvdata(dev);
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return clk_bulk_prepare_enable(data->num_clks, data->clks);
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}
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static int cdns_imx_suspend(struct device *dev)
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{
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struct cdns_imx *data = dev_get_drvdata(dev);
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clk_bulk_disable_unprepare(data->num_clks, data->clks);
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return 0;
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}
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/* Indicate if the controller was power lost before */
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static inline bool cdns_imx_is_power_lost(struct cdns_imx *data)
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{
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u32 value;
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value = cdns_imx_readl(data, USB3_CORE_CTRL1);
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if ((value & SW_RESET_MASK) == ALL_SW_RESET)
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return true;
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else
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return false;
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}
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static int __maybe_unused cdns_imx_system_suspend(struct device *dev)
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{
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pm_runtime_put_sync(dev);
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return 0;
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}
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static int __maybe_unused cdns_imx_system_resume(struct device *dev)
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{
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struct cdns_imx *data = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_resume_and_get(dev);
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if (ret < 0) {
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dev_err(dev, "Could not get runtime PM.\n");
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return ret;
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}
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if (cdns_imx_is_power_lost(data)) {
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dev_dbg(dev, "resume from power lost\n");
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ret = cdns_imx_noncore_init(data);
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if (ret)
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cdns_imx_suspend(dev);
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}
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return ret;
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}
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#else
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static int cdns_imx_platform_suspend(struct device *dev,
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bool suspend, bool wakeup)
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{
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return 0;
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}
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#endif /* CONFIG_PM */
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static const struct dev_pm_ops cdns_imx_pm_ops = {
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SET_RUNTIME_PM_OPS(cdns_imx_suspend, cdns_imx_resume, NULL)
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SET_SYSTEM_SLEEP_PM_OPS(cdns_imx_system_suspend, cdns_imx_system_resume)
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};
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static const struct of_device_id cdns_imx_of_match[] = {
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{ .compatible = "fsl,imx8qm-usb3", },
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{},
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};
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MODULE_DEVICE_TABLE(of, cdns_imx_of_match);
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static struct platform_driver cdns_imx_driver = {
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.probe = cdns_imx_probe,
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.remove_new = cdns_imx_remove,
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.driver = {
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.name = "cdns3-imx",
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.of_match_table = cdns_imx_of_match,
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.pm = &cdns_imx_pm_ops,
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},
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};
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module_platform_driver(cdns_imx_driver);
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MODULE_ALIAS("platform:cdns3-imx");
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MODULE_AUTHOR("Peter Chen <peter.chen@nxp.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Cadence USB3 i.MX Glue Layer");
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