original_kernel/arch/mips/cavium-octeon
Charles Hardin 0f731711af mips/octeon: 16-Bit NOR flash was not being detected during boot
The cavium code assumed that all NOR on the boot bus was
an 8-bit NOR part and hardcoded the bankwidth. The simple
solution was to add the code that queries the configuration
register for the width of the bus that has been hardware strapped
to the Cavium. This allows both 8-bit and 16-bit parts to be
discovered during boot.

Acked-by: David Daney <david.daney@cavium.com>
Signed-off-by: Charles Hardin <ckhardin@exablox.com>
Patchwork: http://patchwork.linux-mips.org/patch/4323
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-11-09 11:37:16 +01:00
..
executive MIPS: OCTEON: Update register definitions. 2012-08-31 10:46:53 -07:00
.gitignore MIPS: Octeon: Add device tree source files. 2012-07-23 13:54:52 +01:00
Kconfig MIPS: Cavium: Fix duplicate ARCH_SPARSEMEM_ENABLE in kconfig. 2012-07-19 11:23:43 +02:00
Makefile MIPS: Octeon: Initialize and fixup device tree. 2012-07-23 13:54:52 +01:00
Platform
cpu.c
csrc-octeon.c MIPS: Octeon: Add octeon_io_clk_delay() function. 2012-08-31 11:48:48 -07:00
dma-octeon.c
flash_setup.c mips/octeon: 16-Bit NOR flash was not being detected during boot 2012-11-09 11:37:16 +01:00
octeon-irq.c MIPS: OCTEON: Register ciu/ciu2 as the default irq_domain. 2012-08-31 10:46:54 -07:00
octeon-memcpy.S MIPS: Octeon: Implement Octeon specific __copy_user_inatomic 2012-07-23 13:55:55 +01:00
octeon-platform.c netdev: octeon_mgmt: Convert to use device tree. 2012-07-23 13:54:53 +01:00
octeon_3xxx.dts MIPS: Octeon: Add device tree source files. 2012-07-23 13:54:52 +01:00
octeon_68xx.dts MIPS: Octeon: Add device tree source files. 2012-07-23 13:54:52 +01:00
octeon_boot.h
serial.c MIPS: OCTEON: Fix breakage due to 8250 changes. 2012-08-14 14:54:31 -07:00
setup.c MIPS: Octeon: Add octeon_io_clk_delay() function. 2012-08-31 11:48:48 -07:00
smp.c MIPS: Octeon: delay enable irq to ->smp_finish() 2012-07-19 11:23:44 +02:00