171 lines
3.7 KiB
C
171 lines
3.7 KiB
C
/*
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* Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
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* Author: Yanhua, yanh@lemote.com
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/cpufreq.h>
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#include <linux/platform_device.h>
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#include <asm/clock.h>
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#include <loongson.h>
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static LIST_HEAD(clock_list);
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static DEFINE_SPINLOCK(clock_lock);
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static DEFINE_MUTEX(clock_list_sem);
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/* Minimum CLK support */
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enum {
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DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
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DC_87PT, DC_DISABLE, DC_RESV
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};
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struct cpufreq_frequency_table loongson2_clockmod_table[] = {
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{DC_RESV, CPUFREQ_ENTRY_INVALID},
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{DC_ZERO, CPUFREQ_ENTRY_INVALID},
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{DC_25PT, 0},
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{DC_37PT, 0},
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{DC_50PT, 0},
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{DC_62PT, 0},
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{DC_75PT, 0},
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{DC_87PT, 0},
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{DC_DISABLE, 0},
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{DC_RESV, CPUFREQ_TABLE_END},
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};
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EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
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static struct clk cpu_clk = {
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.name = "cpu_clk",
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.flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
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.rate = 800000000,
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};
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struct clk *clk_get(struct device *dev, const char *id)
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{
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return &cpu_clk;
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}
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EXPORT_SYMBOL(clk_get);
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static void propagate_rate(struct clk *clk)
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{
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struct clk *clkp;
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list_for_each_entry(clkp, &clock_list, node) {
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if (likely(clkp->parent != clk))
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continue;
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if (likely(clkp->ops && clkp->ops->recalc))
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clkp->ops->recalc(clkp);
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if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
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propagate_rate(clkp);
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}
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}
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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return (unsigned long)clk->rate;
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}
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EXPORT_SYMBOL(clk_get_rate);
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void clk_put(struct clk *clk)
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{
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}
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EXPORT_SYMBOL(clk_put);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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return clk_set_rate_ex(clk, rate, 0);
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}
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EXPORT_SYMBOL_GPL(clk_set_rate);
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int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
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{
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int ret = 0;
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int regval;
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int i;
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if (likely(clk->ops && clk->ops->set_rate)) {
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unsigned long flags;
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spin_lock_irqsave(&clock_lock, flags);
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ret = clk->ops->set_rate(clk, rate, algo_id);
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spin_unlock_irqrestore(&clock_lock, flags);
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}
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if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
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propagate_rate(clk);
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for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
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i++) {
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if (loongson2_clockmod_table[i].frequency ==
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CPUFREQ_ENTRY_INVALID)
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continue;
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if (rate == loongson2_clockmod_table[i].frequency)
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break;
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}
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if (rate != loongson2_clockmod_table[i].frequency)
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return -ENOTSUPP;
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clk->rate = rate;
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regval = LOONGSON_CHIPCFG0;
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regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
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LOONGSON_CHIPCFG0 = regval;
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return ret;
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}
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EXPORT_SYMBOL_GPL(clk_set_rate_ex);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (likely(clk->ops && clk->ops->round_rate)) {
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unsigned long flags, rounded;
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spin_lock_irqsave(&clock_lock, flags);
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rounded = clk->ops->round_rate(clk, rate);
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spin_unlock_irqrestore(&clock_lock, flags);
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return rounded;
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}
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return rate;
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}
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EXPORT_SYMBOL_GPL(clk_round_rate);
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/*
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* This is the simple version of Loongson-2 wait, Maybe we need do this in
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* interrupt disabled content
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*/
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DEFINE_SPINLOCK(loongson2_wait_lock);
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void loongson2_cpu_wait(void)
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{
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u32 cpu_freq;
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unsigned long flags;
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spin_lock_irqsave(&loongson2_wait_lock, flags);
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cpu_freq = LOONGSON_CHIPCFG0;
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LOONGSON_CHIPCFG0 &= ~0x7; /* Put CPU into wait mode */
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LOONGSON_CHIPCFG0 = cpu_freq; /* Restore CPU state */
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spin_unlock_irqrestore(&loongson2_wait_lock, flags);
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}
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EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
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MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
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MODULE_DESCRIPTION("cpufreq driver for Loongson 2F");
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MODULE_LICENSE("GPL");
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