190 lines
6.5 KiB
C
190 lines
6.5 KiB
C
/* mb-regs.h: motherboard registers
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*
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* Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_MB_REGS_H
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#define _ASM_MB_REGS_H
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#include <asm/cpu-irqs.h>
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#include <asm/sections.h>
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#include <asm/mem-layout.h>
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#define __region_IO KERNEL_IO_START /* the region from 0xe0000000 to 0xffffffff has suitable
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* protection laid over the top for use in memory-mapped
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* I/O
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*/
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#define __region_CS0 0xff000000 /* Boot ROMs area */
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#ifdef CONFIG_MB93091_VDK
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/*
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* VDK motherboard and CPU card specific stuff
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*/
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#include <asm/mb93091-fpga-irqs.h>
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#define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0
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#define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1
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#define __region_CS2 0xe0000000 /* SLBUS/PCI I/O space */
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#define __region_CS2_M 0x0fffffff /* mask */
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#define __region_CS2_C 0x00000000 /* control */
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#define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */
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#define __region_CS5_M 0x00ffffff
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#define __region_CS5_C 0x00010000
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#define __region_CS7 0xf1000000 /* CB70 CPU-card PCMCIA port I/O space */
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#define __region_CS7_M 0x00ffffff
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#define __region_CS7_C 0x00410701
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#define __region_CS1 0xfc000000 /* SLBUS/PCI bridge control registers */
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#define __region_CS1_M 0x000fffff
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#define __region_CS1_C 0x00000000
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#define __region_CS6 0xfc100000 /* CB70 CPU-card DM9000 LAN I/O space */
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#define __region_CS6_M 0x000fffff
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#define __region_CS6_C 0x00400707
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#define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
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#define __region_CS3_M 0x000fffff
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#define __region_CS3_C 0xc8100000
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#define __region_CS4 0xfd000000 /* CB70 CPU-card extra flash space */
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#define __region_CS4_M 0x00ffffff
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#define __region_CS4_C 0x00000f07
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#define __region_PCI_IO (__region_CS2 + 0x04000000UL)
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#define __region_PCI_MEM (__region_CS2 + 0x08000000UL)
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#define __flush_PCI_writes() \
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do { \
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__builtin_write8((volatile void *) __region_PCI_MEM, 0); \
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} while(0)
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#define __is_PCI_IO(addr) \
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(((unsigned long)(addr) >> 24) - (__region_PCI_IO >> 24) < (0x04000000UL >> 24))
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#define __is_PCI_MEM(addr) \
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((unsigned long)(addr) - __region_PCI_MEM < 0x08000000UL)
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#define __is_PCI_addr(addr) \
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((unsigned long)(addr) - __region_PCI_IO < 0x0c000000UL)
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#define __get_CLKSW() ({ *(volatile unsigned long *)(__region_CS2 + 0x0130000cUL) & 0xffUL; })
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#define __get_CLKIN() (__get_CLKSW() * 125U * 100000U / 24U)
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#ifndef __ASSEMBLY__
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extern int __nongprelbss mb93090_mb00_detected;
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#endif
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#define __addr_LEDS() (__region_CS2 + 0x01200004UL)
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#ifdef CONFIG_MB93090_MB00
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#define __set_LEDS(X) \
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do { \
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if (mb93090_mb00_detected) \
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__builtin_write32((void *) __addr_LEDS(), ~(X)); \
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} while (0)
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#else
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#define __set_LEDS(X)
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#endif
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#define __addr_LCD() (__region_CS2 + 0x01200008UL)
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#define __get_LCD(B) __builtin_read32((volatile void *) (B))
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#define __set_LCD(B,X) __builtin_write32((volatile void *) (B), (X))
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#define LCD_D 0x000000ff /* LCD data bus */
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#define LCD_RW 0x00000100 /* LCD R/W signal */
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#define LCD_RS 0x00000200 /* LCD Register Select */
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#define LCD_E 0x00000400 /* LCD Start Enable Signal */
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#define LCD_CMD_CLEAR (LCD_E|0x001)
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#define LCD_CMD_HOME (LCD_E|0x002)
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#define LCD_CMD_CURSOR_INC (LCD_E|0x004)
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#define LCD_CMD_SCROLL_INC (LCD_E|0x005)
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#define LCD_CMD_CURSOR_DEC (LCD_E|0x006)
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#define LCD_CMD_SCROLL_DEC (LCD_E|0x007)
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#define LCD_CMD_OFF (LCD_E|0x008)
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#define LCD_CMD_ON(CRSR,BLINK) (LCD_E|0x00c|(CRSR<<1)|BLINK)
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#define LCD_CMD_CURSOR_MOVE_L (LCD_E|0x010)
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#define LCD_CMD_CURSOR_MOVE_R (LCD_E|0x014)
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#define LCD_CMD_DISPLAY_SHIFT_L (LCD_E|0x018)
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#define LCD_CMD_DISPLAY_SHIFT_R (LCD_E|0x01c)
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#define LCD_CMD_FUNCSET(DL,N,F) (LCD_E|0x020|(DL<<4)|(N<<3)|(F<<2))
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#define LCD_CMD_SET_CG_ADDR(X) (LCD_E|0x040|X)
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#define LCD_CMD_SET_DD_ADDR(X) (LCD_E|0x080|X)
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#define LCD_CMD_READ_BUSY (LCD_E|LCD_RW)
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#define LCD_DATA_WRITE(X) (LCD_E|LCD_RS|(X))
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#define LCD_DATA_READ (LCD_E|LCD_RS|LCD_RW)
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#else
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/*
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* PDK unit specific stuff
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*/
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#include <asm/mb93093-fpga-irqs.h>
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#define IRQ_CPU_MB93493_0 IRQ_CPU_EXTERNAL0
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#define IRQ_CPU_MB93493_1 IRQ_CPU_EXTERNAL1
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#define __region_CS5 0xf0000000 /* MB93493 CSC area (DAV daughter board) */
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#define __region_CS5_M 0x00ffffff /* mask */
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#define __region_CS5_C 0x00010000 /* control */
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#define __region_CS2 0x20000000 /* FPGA registers */
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#define __region_CS2_M 0x000fffff
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#define __region_CS2_C 0x00000000
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#define __region_CS1 0xfc100000 /* LAN registers */
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#define __region_CS1_M 0x000fffff
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#define __region_CS1_C 0x00010404
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#define __region_CS3 0xfc200000 /* MB93493 CSR area (DAV daughter board) */
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#define __region_CS3_M 0x000fffff
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#define __region_CS3_C 0xc8000000
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#define __region_CS4 0xfd000000 /* extra ROMs area */
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#define __region_CS4_M 0x00ffffff
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#define __region_CS4_C 0x00000f07
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#define __region_CS6 0xfe000000 /* not used - hide behind CPU resource I/O regs */
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#define __region_CS6_M 0x000fffff
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#define __region_CS6_C 0x00000f07
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#define __region_CS7 0xfe000000 /* not used - hide behind CPU resource I/O regs */
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#define __region_CS7_M 0x000fffff
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#define __region_CS7_C 0x00000f07
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#define __is_PCI_IO(addr) 0 /* no PCI */
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#define __is_PCI_MEM(addr) 0
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#define __is_PCI_addr(addr) 0
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#define __region_PCI_IO 0
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#define __region_PCI_MEM 0
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#define __flush_PCI_writes() do { } while(0)
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#define __get_CLKSW() 0UL
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#define __get_CLKIN() 66000000UL
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#define __addr_LEDS() (__region_CS2 + 0x00000023UL)
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#define __set_LEDS(X) __builtin_write8((volatile void *) __addr_LEDS(), (X))
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#define __addr_FPGATR() (__region_CS2 + 0x00000030UL)
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#define __set_FPGATR(X) __builtin_write32((volatile void *) __addr_FPGATR(), (X))
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#define __get_FPGATR() __builtin_read32((volatile void *) __addr_FPGATR())
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#define MB93093_FPGA_FPGATR_AUDIO_CLK 0x00000003
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#define __set_FPGATR_AUDIO_CLK(V) \
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__set_FPGATR((__get_FPGATR() & ~MB93093_FPGA_FPGATR_AUDIO_CLK) | (V))
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#define MB93093_FPGA_FPGATR_AUDIO_CLK_OFF 0x0
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#define MB93093_FPGA_FPGATR_AUDIO_CLK_11MHz 0x1
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#define MB93093_FPGA_FPGATR_AUDIO_CLK_12MHz 0x2
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#define MB93093_FPGA_FPGATR_AUDIO_CLK_02MHz 0x3
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#define MB93093_FPGA_SWR_PUSHSWMASK (0x1F<<26)
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#define MB93093_FPGA_SWR_PUSHSW4 (1<<29)
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#define __addr_FPGA_SWR ((volatile void *)(__region_CS2 + 0x28UL))
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#define __get_FPGA_PUSHSW1_5() (__builtin_read32(__addr_FPGA_SWR) & MB93093_FPGA_SWR_PUSHSWMASK)
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#endif
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#endif /* _ASM_MB_REGS_H */
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