216 lines
9.8 KiB
C
216 lines
9.8 KiB
C
/*
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* Defines x86 CPU feature bits
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*/
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#ifndef _ASM_X86_CPUFEATURE_H
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#define _ASM_X86_CPUFEATURE_H
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#include <asm/required-features.h>
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#define NCAPINTS 8 /* N 32-bit words worth of info */
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/* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
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#define X86_FEATURE_FPU (0*32+ 0) /* Onboard FPU */
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#define X86_FEATURE_VME (0*32+ 1) /* Virtual Mode Extensions */
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#define X86_FEATURE_DE (0*32+ 2) /* Debugging Extensions */
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#define X86_FEATURE_PSE (0*32+ 3) /* Page Size Extensions */
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#define X86_FEATURE_TSC (0*32+ 4) /* Time Stamp Counter */
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#define X86_FEATURE_MSR (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
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#define X86_FEATURE_PAE (0*32+ 6) /* Physical Address Extensions */
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#define X86_FEATURE_MCE (0*32+ 7) /* Machine Check Architecture */
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#define X86_FEATURE_CX8 (0*32+ 8) /* CMPXCHG8 instruction */
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#define X86_FEATURE_APIC (0*32+ 9) /* Onboard APIC */
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#define X86_FEATURE_SEP (0*32+11) /* SYSENTER/SYSEXIT */
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#define X86_FEATURE_MTRR (0*32+12) /* Memory Type Range Registers */
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#define X86_FEATURE_PGE (0*32+13) /* Page Global Enable */
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#define X86_FEATURE_MCA (0*32+14) /* Machine Check Architecture */
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#define X86_FEATURE_CMOV (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
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#define X86_FEATURE_PAT (0*32+16) /* Page Attribute Table */
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#define X86_FEATURE_PSE36 (0*32+17) /* 36-bit PSEs */
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#define X86_FEATURE_PN (0*32+18) /* Processor serial number */
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#define X86_FEATURE_CLFLSH (0*32+19) /* Supports the CLFLUSH instruction */
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#define X86_FEATURE_DS (0*32+21) /* Debug Store */
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#define X86_FEATURE_ACPI (0*32+22) /* ACPI via MSR */
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#define X86_FEATURE_MMX (0*32+23) /* Multimedia Extensions */
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#define X86_FEATURE_FXSR (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
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/* of FPU context), and CR4.OSFXSR available */
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#define X86_FEATURE_XMM (0*32+25) /* Streaming SIMD Extensions */
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#define X86_FEATURE_XMM2 (0*32+26) /* Streaming SIMD Extensions-2 */
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#define X86_FEATURE_SELFSNOOP (0*32+27) /* CPU self snoop */
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#define X86_FEATURE_HT (0*32+28) /* Hyper-Threading */
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#define X86_FEATURE_ACC (0*32+29) /* Automatic clock control */
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#define X86_FEATURE_IA64 (0*32+30) /* IA-64 processor */
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/* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/* Don't duplicate feature flags which are redundant with Intel! */
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#define X86_FEATURE_SYSCALL (1*32+11) /* SYSCALL/SYSRET */
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#define X86_FEATURE_MP (1*32+19) /* MP Capable. */
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#define X86_FEATURE_NX (1*32+20) /* Execute Disable */
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#define X86_FEATURE_MMXEXT (1*32+22) /* AMD MMX extensions */
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#define X86_FEATURE_GBPAGES (1*32+26) /* GB pages */
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#define X86_FEATURE_RDTSCP (1*32+27) /* RDTSCP */
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#define X86_FEATURE_LM (1*32+29) /* Long Mode (x86-64) */
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#define X86_FEATURE_3DNOWEXT (1*32+30) /* AMD 3DNow! extensions */
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#define X86_FEATURE_3DNOW (1*32+31) /* 3DNow! */
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/* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
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#define X86_FEATURE_RECOVERY (2*32+ 0) /* CPU in recovery mode */
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#define X86_FEATURE_LONGRUN (2*32+ 1) /* Longrun power control */
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#define X86_FEATURE_LRTI (2*32+ 3) /* LongRun table interface */
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/* Other features, Linux-defined mapping, word 3 */
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/* This range is used for feature bits which conflict or are synthesized */
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#define X86_FEATURE_CXMMX (3*32+ 0) /* Cyrix MMX extensions */
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#define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */
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#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
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/* cpu types for specific tunings: */
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#define X86_FEATURE_K8 (3*32+ 4) /* Opteron, Athlon64 */
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#define X86_FEATURE_K7 (3*32+ 5) /* Athlon */
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#define X86_FEATURE_P3 (3*32+ 6) /* P3 */
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#define X86_FEATURE_P4 (3*32+ 7) /* P4 */
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#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
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#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
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#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
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#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
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#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
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#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
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/* 14 free */
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/* 15 free */
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#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
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#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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#define X86_FEATURE_MWAIT (4*32+ 3) /* Monitor/Mwait support */
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#define X86_FEATURE_DSCPL (4*32+ 4) /* CPL Qualified Debug Store */
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#define X86_FEATURE_EST (4*32+ 7) /* Enhanced SpeedStep */
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#define X86_FEATURE_TM2 (4*32+ 8) /* Thermal Monitor 2 */
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#define X86_FEATURE_CID (4*32+10) /* Context ID */
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#define X86_FEATURE_CX16 (4*32+13) /* CMPXCHG16B */
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#define X86_FEATURE_XTPR (4*32+14) /* Send Task Priority Messages */
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#define X86_FEATURE_DCA (4*32+18) /* Direct Cache Access */
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/* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
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#define X86_FEATURE_XSTORE (5*32+ 2) /* on-CPU RNG present (xstore insn) */
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#define X86_FEATURE_XSTORE_EN (5*32+ 3) /* on-CPU RNG enabled */
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#define X86_FEATURE_XCRYPT (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
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#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
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#define X86_FEATURE_ACE2 (5*32+ 8) /* Advanced Cryptography Engine v2 */
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#define X86_FEATURE_ACE2_EN (5*32+ 9) /* ACE v2 enabled */
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#define X86_FEATURE_PHE (5*32+ 10) /* PadLock Hash Engine */
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#define X86_FEATURE_PHE_EN (5*32+ 11) /* PHE enabled */
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#define X86_FEATURE_PMM (5*32+ 12) /* PadLock Montgomery Multiplier */
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#define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */
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/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
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#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
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#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
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/*
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* Auxiliary flags: Linux defined - For features scattered in various
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* CPUID levels like 0x6, 0xA etc
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*/
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#define X86_FEATURE_IDA (7*32+ 0) /* Intel Dynamic Acceleration */
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#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
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#include <linux/bitops.h>
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extern const char * const x86_cap_flags[NCAPINTS*32];
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extern const char * const x86_power_flags[32];
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#define cpu_has(c, bit) \
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(__builtin_constant_p(bit) && \
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( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0)) || \
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(((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1)) || \
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(((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2)) || \
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(((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3)) || \
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(((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4)) || \
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(((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5)) || \
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(((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6)) || \
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(((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7)) ) \
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? 1 : \
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test_bit(bit, (unsigned long *)((c)->x86_capability)))
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#define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit)
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#define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability))
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#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
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#define setup_clear_cpu_cap(bit) do { \
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clear_cpu_cap(&boot_cpu_data, bit); \
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set_bit(bit, cleared_cpu_caps); \
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} while (0)
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#define setup_force_cpu_cap(bit) do { \
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set_cpu_cap(&boot_cpu_data, bit); \
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clear_bit(bit, cleared_cpu_caps); \
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} while (0)
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#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
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#define cpu_has_vme boot_cpu_has(X86_FEATURE_VME)
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#define cpu_has_de boot_cpu_has(X86_FEATURE_DE)
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#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
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#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
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#define cpu_has_pae boot_cpu_has(X86_FEATURE_PAE)
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#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
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#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
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#define cpu_has_sep boot_cpu_has(X86_FEATURE_SEP)
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#define cpu_has_mtrr boot_cpu_has(X86_FEATURE_MTRR)
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#define cpu_has_mmx boot_cpu_has(X86_FEATURE_MMX)
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#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
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#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
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#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
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#define cpu_has_xmm3 boot_cpu_has(X86_FEATURE_XMM3)
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#define cpu_has_ht boot_cpu_has(X86_FEATURE_HT)
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#define cpu_has_mp boot_cpu_has(X86_FEATURE_MP)
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#define cpu_has_nx boot_cpu_has(X86_FEATURE_NX)
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#define cpu_has_k6_mtrr boot_cpu_has(X86_FEATURE_K6_MTRR)
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#define cpu_has_cyrix_arr boot_cpu_has(X86_FEATURE_CYRIX_ARR)
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#define cpu_has_centaur_mcr boot_cpu_has(X86_FEATURE_CENTAUR_MCR)
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#define cpu_has_xstore boot_cpu_has(X86_FEATURE_XSTORE)
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#define cpu_has_xstore_enabled boot_cpu_has(X86_FEATURE_XSTORE_EN)
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#define cpu_has_xcrypt boot_cpu_has(X86_FEATURE_XCRYPT)
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#define cpu_has_xcrypt_enabled boot_cpu_has(X86_FEATURE_XCRYPT_EN)
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#define cpu_has_ace2 boot_cpu_has(X86_FEATURE_ACE2)
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#define cpu_has_ace2_enabled boot_cpu_has(X86_FEATURE_ACE2_EN)
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#define cpu_has_phe boot_cpu_has(X86_FEATURE_PHE)
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#define cpu_has_phe_enabled boot_cpu_has(X86_FEATURE_PHE_EN)
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#define cpu_has_pmm boot_cpu_has(X86_FEATURE_PMM)
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#define cpu_has_pmm_enabled boot_cpu_has(X86_FEATURE_PMM_EN)
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#define cpu_has_ds boot_cpu_has(X86_FEATURE_DS)
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#define cpu_has_pebs boot_cpu_has(X86_FEATURE_PEBS)
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#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLSH)
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#define cpu_has_bts boot_cpu_has(X86_FEATURE_BTS)
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#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
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#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
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# define cpu_has_invlpg 1
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#else
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# define cpu_has_invlpg (boot_cpu_data.x86 > 3)
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#endif
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#ifdef CONFIG_X86_64
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#undef cpu_has_vme
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#define cpu_has_vme 0
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#undef cpu_has_pae
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#define cpu_has_pae ___BUG___
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#undef cpu_has_mp
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#define cpu_has_mp 1
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#undef cpu_has_k6_mtrr
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#define cpu_has_k6_mtrr 0
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#undef cpu_has_cyrix_arr
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#define cpu_has_cyrix_arr 0
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#undef cpu_has_centaur_mcr
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#define cpu_has_centaur_mcr 0
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#endif /* CONFIG_X86_64 */
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#endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
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#endif /* _ASM_X86_CPUFEATURE_H */
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