326 lines
9.8 KiB
C
326 lines
9.8 KiB
C
/*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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* Copyright (C) Ashok Raj <ashok.raj@intel.com>
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* Copyright (C) Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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*/
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#ifndef _INTEL_IOMMU_H_
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#define _INTEL_IOMMU_H_
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#include <linux/types.h>
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#include <linux/msi.h>
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#include "iova.h"
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#include <linux/io.h>
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/*
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* Intel IOMMU register specification per version 1.0 public spec.
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*/
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#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
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#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
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#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
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#define DMAR_GCMD_REG 0x18 /* Global command register */
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#define DMAR_GSTS_REG 0x1c /* Global status register */
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#define DMAR_RTADDR_REG 0x20 /* Root entry table */
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#define DMAR_CCMD_REG 0x28 /* Context command reg */
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#define DMAR_FSTS_REG 0x34 /* Fault Status register */
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#define DMAR_FECTL_REG 0x38 /* Fault control register */
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#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
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#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
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#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
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#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
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#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
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#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
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#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
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#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
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#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
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#define OFFSET_STRIDE (9)
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/*
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#define dmar_readl(dmar, reg) readl(dmar + reg)
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#define dmar_readq(dmar, reg) ({ \
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u32 lo, hi; \
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lo = readl(dmar + reg); \
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hi = readl(dmar + reg + 4); \
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(((u64) hi) << 32) + lo; })
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*/
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static inline u64 dmar_readq(void __iomem *addr)
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{
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u32 lo, hi;
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lo = readl(addr);
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hi = readl(addr + 4);
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return (((u64) hi) << 32) + lo;
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}
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static inline void dmar_writeq(void __iomem *addr, u64 val)
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{
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writel((u32)val, addr);
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writel((u32)(val >> 32), addr + 4);
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}
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#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
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#define DMAR_VER_MINOR(v) ((v) & 0x0f)
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/*
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* Decoding Capability Register
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*/
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#define cap_read_drain(c) (((c) >> 55) & 1)
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#define cap_write_drain(c) (((c) >> 54) & 1)
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#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
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#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
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#define cap_pgsel_inv(c) (((c) >> 39) & 1)
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#define cap_super_page_val(c) (((c) >> 34) & 0xf)
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#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
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* OFFSET_STRIDE) + 21)
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#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
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#define cap_max_fault_reg_offset(c) \
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(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
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#define cap_zlr(c) (((c) >> 22) & 1)
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#define cap_isoch(c) (((c) >> 23) & 1)
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#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
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#define cap_sagaw(c) (((c) >> 8) & 0x1f)
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#define cap_caching_mode(c) (((c) >> 7) & 1)
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#define cap_phmr(c) (((c) >> 6) & 1)
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#define cap_plmr(c) (((c) >> 5) & 1)
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#define cap_rwbf(c) (((c) >> 4) & 1)
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#define cap_afl(c) (((c) >> 3) & 1)
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#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
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/*
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* Extended Capability Register
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*/
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#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
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#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
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#define ecap_max_iotlb_offset(e) \
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(ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
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#define ecap_coherent(e) ((e) & 0x1)
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/* IOTLB_REG */
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#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
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#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
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#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
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#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
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#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
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#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
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#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
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#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
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#define DMA_TLB_IVT (((u64)1) << 63)
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#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
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#define DMA_TLB_MAX_SIZE (0x3f)
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/* GCMD_REG */
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#define DMA_GCMD_TE (((u32)1) << 31)
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#define DMA_GCMD_SRTP (((u32)1) << 30)
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#define DMA_GCMD_SFL (((u32)1) << 29)
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#define DMA_GCMD_EAFL (((u32)1) << 28)
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#define DMA_GCMD_WBF (((u32)1) << 27)
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/* GSTS_REG */
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#define DMA_GSTS_TES (((u32)1) << 31)
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#define DMA_GSTS_RTPS (((u32)1) << 30)
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#define DMA_GSTS_FLS (((u32)1) << 29)
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#define DMA_GSTS_AFLS (((u32)1) << 28)
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#define DMA_GSTS_WBFS (((u32)1) << 27)
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/* CCMD_REG */
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#define DMA_CCMD_ICC (((u64)1) << 63)
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#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
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#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
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#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
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#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
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#define DMA_CCMD_MASK_NOBIT 0
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#define DMA_CCMD_MASK_1BIT 1
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#define DMA_CCMD_MASK_2BIT 2
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#define DMA_CCMD_MASK_3BIT 3
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#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
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#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
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/* FECTL_REG */
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#define DMA_FECTL_IM (((u32)1) << 31)
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/* FSTS_REG */
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#define DMA_FSTS_PPF ((u32)2)
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#define DMA_FSTS_PFO ((u32)1)
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#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
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/* FRCD_REG, 32 bits access */
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#define DMA_FRCD_F (((u32)1) << 31)
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#define dma_frcd_type(d) ((d >> 30) & 1)
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#define dma_frcd_fault_reason(c) (c & 0xff)
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#define dma_frcd_source_id(c) (c & 0xffff)
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#define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
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/*
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* 0: Present
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* 1-11: Reserved
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* 12-63: Context Ptr (12 - (haw-1))
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* 64-127: Reserved
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*/
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struct root_entry {
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u64 val;
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u64 rsvd1;
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};
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#define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
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static inline bool root_present(struct root_entry *root)
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{
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return (root->val & 1);
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}
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static inline void set_root_present(struct root_entry *root)
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{
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root->val |= 1;
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}
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static inline void set_root_value(struct root_entry *root, unsigned long value)
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{
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root->val |= value & PAGE_MASK_4K;
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}
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struct context_entry;
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static inline struct context_entry *
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get_context_addr_from_root(struct root_entry *root)
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{
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return (struct context_entry *)
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(root_present(root)?phys_to_virt(
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root->val & PAGE_MASK_4K):
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NULL);
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}
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/*
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* low 64 bits:
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* 0: present
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* 1: fault processing disable
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* 2-3: translation type
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* 12-63: address space root
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* high 64 bits:
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* 0-2: address width
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* 3-6: aval
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* 8-23: domain id
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*/
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struct context_entry {
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u64 lo;
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u64 hi;
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};
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#define context_present(c) ((c).lo & 1)
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#define context_fault_disable(c) (((c).lo >> 1) & 1)
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#define context_translation_type(c) (((c).lo >> 2) & 3)
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#define context_address_root(c) ((c).lo & PAGE_MASK_4K)
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#define context_address_width(c) ((c).hi & 7)
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#define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
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#define context_set_present(c) do {(c).lo |= 1;} while (0)
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#define context_set_fault_enable(c) \
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do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
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#define context_set_translation_type(c, val) \
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do { \
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(c).lo &= (((u64)-1) << 4) | 3; \
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(c).lo |= ((val) & 3) << 2; \
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} while (0)
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#define CONTEXT_TT_MULTI_LEVEL 0
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#define context_set_address_root(c, val) \
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do {(c).lo |= (val) & PAGE_MASK_4K;} while (0)
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#define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
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#define context_set_domain_id(c, val) \
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do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
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#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
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/*
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* 0: readable
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* 1: writable
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* 2-6: reserved
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* 7: super page
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* 8-11: available
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* 12-63: Host physcial address
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*/
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struct dma_pte {
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u64 val;
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};
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#define dma_clear_pte(p) do {(p).val = 0;} while (0)
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#define DMA_PTE_READ (1)
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#define DMA_PTE_WRITE (2)
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#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
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#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
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#define dma_set_pte_prot(p, prot) \
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do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
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#define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
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#define dma_set_pte_addr(p, addr) do {\
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(p).val |= ((addr) & PAGE_MASK_4K); } while (0)
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#define dma_pte_present(p) (((p).val & 3) != 0)
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struct intel_iommu;
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struct dmar_domain {
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int id; /* domain id */
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struct intel_iommu *iommu; /* back pointer to owning iommu */
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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struct dma_pte *pgd; /* virtual address */
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spinlock_t mapping_lock; /* page table lock */
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int gaw; /* max guest address width */
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/* adjusted guest address width, 0 is level 2 30-bit */
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int agaw;
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#define DOMAIN_FLAG_MULTIPLE_DEVICES 1
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int flags;
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};
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/* PCI domain-device relationship */
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struct device_domain_info {
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struct list_head link; /* link to domain siblings */
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struct list_head global; /* link to global list */
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u8 bus; /* PCI bus numer */
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u8 devfn; /* PCI devfn number */
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struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
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struct dmar_domain *domain; /* pointer to domain */
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};
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extern int init_dmars(void);
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struct intel_iommu {
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void __iomem *reg; /* Pointer to hardware regs, virtual addr */
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u64 cap;
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u64 ecap;
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unsigned long *domain_ids; /* bitmap of domains */
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struct dmar_domain **domains; /* ptr to domains */
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int seg;
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u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
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spinlock_t lock; /* protect context, domain ids */
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spinlock_t register_lock; /* protect register handling */
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struct root_entry *root_entry; /* virtual address */
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unsigned int irq;
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unsigned char name[7]; /* Device Name */
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struct msi_msg saved_msg;
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struct sys_device sysdev;
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};
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#ifndef CONFIG_DMAR_GFX_WA
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static inline void iommu_prepare_gfx_mapping(void)
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{
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return;
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}
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#endif /* !CONFIG_DMAR_GFX_WA */
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#endif
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