Ralf Baechle cce335ae47 [MIPS] 64-bit Sibyte kernels need DMA32. ... Sibyte SOCs only have 32-bit PCI. Due to the sparse use of the address space only the first 1GB of memory is mapped at physical addresses below 1GB. If a system has more than 1GB of memory 32-bit DMA will not be able to reach all of it. For now this patch is good enough to keep Sibyte users happy but it seems eventually something like swiotlb will be needed for Sibyte. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2007-11-26 17:26:14 +00:00
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Makefile	…
c-r3k.c	[MIPS] c-r3k: Implement flush_cache_range()	2007-10-29 19:35:36 +00:00
c-r4k.c	[MIPS] Sibyte: resurrect old cache hack.	2007-11-15 23:21:48 +00:00
c-tx39.c	…
cache.c	Remove dma_cache_(wback|inv|wback_inv) functions	2007-10-17 08:42:57 -07:00
cerr-sb1.c	[MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.	2007-11-15 23:21:49 +00:00
cex-gen.S	…
cex-sb1.S	…
dma-default.c	[MIPS] 64-bit Sibyte kernels need DMA32.	2007-11-26 17:26:14 +00:00
extable.c	…
fault.c	pid namespaces: define is_global_init() and is_container_init()	2007-10-19 11:53:37 -07:00
highmem.c	…
init.c	[MIPS] 64-bit Sibyte kernels need DMA32.	2007-11-26 17:26:14 +00:00
ioremap.c	…
pg-r4k.c	…
pg-sb1.c	…
pgtable-32.c	…
pgtable-64.c	…
pgtable.c	…
sc-ip22.c	…
sc-mips.c	…
sc-r5k.c	…
sc-rm7k.c	…
tlb-r3k.c	…
tlb-r4k.c	…
tlb-r8k.c	…
tlbex-fault.S	…
tlbex.c	…