276 lines
9.4 KiB
C
276 lines
9.4 KiB
C
/*
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* xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
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*
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* This header file is sometimes referred to as the "compile-time HAL" or CHAL.
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* It was generated for a specific Xtensa processor configuration,
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* and furthermore for a specific set of TIE source files that extend
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* basic core functionality.
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*
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* Source for configuration-independent binaries (which link in a
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* configuration-specific HAL library) must NEVER include this file.
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* It is perfectly normal, however, for the HAL source itself to include this file.
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*/
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/*
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* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2.1 of the GNU Lesser General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Further, this software is distributed without any warranty that it is
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* free of the rightful claim of any third person regarding infringement
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* or the like. Any license provided herein, whether implied or
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* otherwise, applies only to this software file. Patent licenses, if
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* any, provided herein do not apply to combinations of this program with
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* other software, or any other product whatsoever.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
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* USA.
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*/
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#ifndef XTENSA_CONFIG_TIE_H
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#define XTENSA_CONFIG_TIE_H
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#include <xtensa/hal.h>
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/*----------------------------------------------------------------------
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GENERAL
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----------------------------------------------------------------------*/
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/*
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* Separators for macros that expand into arrays.
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* These can be predefined by files that #include this one,
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* when different separators are required.
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*/
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/* Element separator for macros that expand into 1-dimensional arrays: */
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#ifndef XCHAL_SEP
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#define XCHAL_SEP ,
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#endif
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/* Array separator for macros that expand into 2-dimensional arrays: */
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#ifndef XCHAL_SEP2
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#define XCHAL_SEP2 },{
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#endif
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/*----------------------------------------------------------------------
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COPROCESSORS and EXTRA STATE
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----------------------------------------------------------------------*/
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#define XCHAL_CP_NUM 0 /* number of coprocessors */
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#define XCHAL_CP_MAX 0 /* max coprocessor id plus one (0 if none) */
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#define XCHAL_CP_MASK 0x00 /* bitmask of coprocessors by id */
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/* Space for coprocessors' state save areas: */
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#define XCHAL_CP0_SA_SIZE 0
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#define XCHAL_CP1_SA_SIZE 0
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#define XCHAL_CP2_SA_SIZE 0
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#define XCHAL_CP3_SA_SIZE 0
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#define XCHAL_CP4_SA_SIZE 0
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#define XCHAL_CP5_SA_SIZE 0
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#define XCHAL_CP6_SA_SIZE 0
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#define XCHAL_CP7_SA_SIZE 0
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/* Minimum required alignments of CP state save areas: */
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#define XCHAL_CP0_SA_ALIGN 1
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#define XCHAL_CP1_SA_ALIGN 1
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#define XCHAL_CP2_SA_ALIGN 1
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#define XCHAL_CP3_SA_ALIGN 1
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#define XCHAL_CP4_SA_ALIGN 1
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#define XCHAL_CP5_SA_ALIGN 1
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#define XCHAL_CP6_SA_ALIGN 1
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#define XCHAL_CP7_SA_ALIGN 1
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/* Indexing macros: */
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#define _XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE
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#define XCHAL_CP_SA_SIZE(n) _XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */
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#define _XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN
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#define XCHAL_CP_SA_ALIGN(n) _XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */
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/* Space for "extra" state (user special registers and non-cp TIE) save area: */
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#define XCHAL_EXTRA_SA_SIZE 0
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#define XCHAL_EXTRA_SA_ALIGN 1
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/* Total save area size (extra + all coprocessors) */
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/* (not useful until xthal_{save,restore}_all_extra() is implemented, */
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/* but included for Tor2 beta; doesn't account for alignment!): */
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#define XCHAL_CPEXTRA_SA_SIZE_TOR2 0 /* Tor2Beta temporary definition -- do not use */
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/* Combined required alignment for all CP and EXTRA state save areas */
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/* (does not include required alignment for any base config registers): */
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#define XCHAL_CPEXTRA_SA_ALIGN 1
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/* ... */
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#ifdef _ASMLANGUAGE
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/*
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* Assembly-language specific definitions (assembly macros, etc.).
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*/
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#include <xtensa/config/specreg.h>
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/********************
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* Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
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*/
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/* (none) */
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/********************
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* Macros to create functions that save and restore all EXTRA (non-coprocessor) state
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* (does not include zero-overhead loop registers and non-optional registers).
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*/
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/*
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* Macro that expands to the body of a function that
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* stores the extra (non-coprocessor) optional/custom state.
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* Entry: a2 = ptr to save area in which to save extra state
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* Exit: any register a2-a15 (?) may have been clobbered.
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*/
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.macro xchal_extra_store_funcbody
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.endm
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/*
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* Macro that expands to the body of a function that
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* loads the extra (non-coprocessor) optional/custom state.
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* Entry: a2 = ptr to save area from which to restore extra state
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* Exit: any register a2-a15 (?) may have been clobbered.
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*/
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.macro xchal_extra_load_funcbody
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.endm
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/********************
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* Macros to save and restore the state of each TIE coprocessor.
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*/
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/********************
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* Macros to create functions that save and restore the state of *any* TIE coprocessor.
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*/
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/*
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* Macro that expands to the body of a function
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* that stores the selected coprocessor's state (registers etc).
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* Entry: a2 = ptr to save area in which to save cp state
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* a3 = coprocessor number
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* Exit: any register a2-a15 (?) may have been clobbered.
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*/
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.macro xchal_cpi_store_funcbody
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.endm
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/*
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* Macro that expands to the body of a function
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* that loads the selected coprocessor's state (registers etc).
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* Entry: a2 = ptr to save area from which to restore cp state
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* a3 = coprocessor number
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* Exit: any register a2-a15 (?) may have been clobbered.
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*/
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.macro xchal_cpi_load_funcbody
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.endm
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#endif /*_ASMLANGUAGE*/
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/*
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* Contents of save areas in terms of libdb register numbers.
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* NOTE: CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
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* it is up to the user of this header file to define these macros
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* usefully before each expansion of the CONTENTS_LIBDB macros.
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* (Fields rsv[123] are reserved for future additions; they are currently
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* set to zero but may be set to some useful values in the future.)
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*
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* CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
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* CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
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* CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
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*/
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#define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_EXTRA_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */
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#define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
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#define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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#if 0 /* is there something equivalent for user TIE? */
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#define XCHAL_CORE_ID "linux_be" /* configuration's alphanumeric core identifier
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(CoreID) set in the Xtensa Processor Generator */
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#define XCHAL_BUILD_UNIQUE_ID 0x00003256 /* software build-unique ID (22-bit) */
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/* These definitions describe the hardware targeted by this software: */
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#define XCHAL_HW_CONFIGID0 0xC103D1FF /* config ID reg 0 value (upper 32 of 64 bits) */
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#define XCHAL_HW_CONFIGID1 0x00803256 /* config ID reg 1 value (lower 32 of 64 bits) */
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#define XCHAL_CONFIGID0 XCHAL_HW_CONFIGID0 /* for backward compatibility only -- don't use! */
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#define XCHAL_CONFIGID1 XCHAL_HW_CONFIGID1 /* for backward compatibility only -- don't use! */
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#define XCHAL_HW_RELEASE_MAJOR 1050 /* major release of targeted hardware */
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#define XCHAL_HW_RELEASE_MINOR 1 /* minor release of targeted hardware */
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#define XCHAL_HW_RELEASE_NAME "T1050.1" /* full release name of targeted hardware */
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#define XTHAL_HW_REL_T1050 1
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#define XTHAL_HW_REL_T1050_1 1
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#define XCHAL_HW_CONFIGID_RELIABLE 1
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#endif /*0*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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#if 0 /* these probably don't belong here, but are related to or implemented using TIE */
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#define XCHAL_HAVE_BOOLEANS 0 /* 1 if booleans option configured, 0 otherwise */
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/* Misc instructions: */
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#define XCHAL_HAVE_MUL32 0 /* 1 if 32-bit integer multiply option configured, 0 otherwise */
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#define XCHAL_HAVE_MUL32_HIGH 0 /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
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#define XCHAL_HAVE_FP 0 /* 1 if floating point option configured, 0 otherwise */
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#endif /*0*/
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#endif /*XTENSA_CONFIG_TIE_H*/
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