349 lines
10 KiB
C
349 lines
10 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* IT8172 system controller defines.
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*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __IT8172__H__
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#define __IT8172__H__
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#include <asm/addrspace.h>
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#define IT8172_BASE 0x18000000
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#define IT8172_PCI_IO_BASE 0x14000000
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#define IT8172_PCI_MEM_BASE 0x10000000
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// System registers offsets from IT8172_BASE
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#define IT_CMFPCR 0x0
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#define IT_DSRR 0x2
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#define IT_PCDCR 0x4
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#define IT_SPLLCR 0x6
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#define IT_CIDR 0x10
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#define IT_CRNR 0x12
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#define IT_CPUTR 0x14
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#define IT_CTCR 0x16
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#define IT_SDPR 0xF0
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// Power management register offset from IT8172_PCI_IO_BASE
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// Power Management Device Standby Register
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#define IT_PM_DSR 0x15800
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#define IT_PM_DSR_TMR0SB 0x0001
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#define IT_PM_DSR_TMR1SB 0x0002
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#define IT_PM_DSR_CIR0SB 0x0004
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#define IT_PM_DSR_CIR1SB 0x0008
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#define IT_PM_DSR_SCR0SB 0x0010
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#define IT_PM_DSR_SCR1SB 0x0020
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#define IT_PM_DSR_PPSB 0x0040
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#define IT_PM_DSR_I2CSB 0x0080
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#define IT_PM_DSR_UARTSB 0x0100
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#define IT_PM_DSR_IDESB 0x0200
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#define IT_PM_DSR_ACSB 0x0400
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#define IT_PM_DSR_M68KSB 0x0800
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// Power Management PCI Device Software Reset Register
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#define IT_PM_PCISR 0x15802
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#define IT_PM_PCISR_IDESR 0x0001
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#define IT_PM_PCISR_CDMASR 0x0002
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#define IT_PM_PCISR_USBSR 0x0004
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#define IT_PM_PCISR_DMASR 0x0008
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#define IT_PM_PCISR_ACSR 0x0010
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#define IT_PM_PCISR_MEMSR 0x0020
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#define IT_PM_PCISR_68KSR 0x0040
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// PCI Configuration address and data register offsets
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// from IT8172_BASE
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#define IT_CONFADDR 0x4000
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#define IT_BUSNUM_SHF 16
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#define IT_DEVNUM_SHF 11
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#define IT_FUNCNUM_SHF 8
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#define IT_REGNUM_SHF 2
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#define IT_CONFDATA 0x4004
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// PCI configuration header common register offsets
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#define IT_VID 0x00
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#define IT_DID 0x02
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#define IT_PCICMD 0x04
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#define IT_PCISTS 0x06
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#define IT_RID 0x08
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#define IT_CLASSC 0x09
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#define IT_HEADT 0x0E
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#define IT_SERIRQC 0x49
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// PCI to Internal/LPC Bus Bridge configuration header register offset
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#define IT_P2I_BCR 0x4C
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#define IT_P2I_D0IOSC 0x50
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#define IT_P2I_D1IOSC 0x54
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#define IT_P2I_D2IOSC 0x58
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#define IT_P2I_D3IOSC 0x5C
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#define IT_P2I_D4IOSC 0x60
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#define IT_P2I_D5IOSC 0x64
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#define IT_P2I_D6IOSC 0x68
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#define IT_P2I_D7IOSC 0x6C
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#define IT_P2I_D8IOSC 0x70
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#define IT_P2I_D9IOSC 0x74
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#define IT_P2I_D10IOSC 0x78
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#define IT_P2I_D11IOSC 0x7C
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// Memory controller register offsets from IT8172_BASE
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#define IT_MC_SDRMR 0x1000
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#define IT_MC_SDRTR 0x1004
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#define IT_MC_MCR 0x1008
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#define IT_MC_SDTYPE 0x100C
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#define IT_MC_WPBA 0x1010
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#define IT_MC_WPTA 0x1014
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#define IT_MC_HATR 0x1018
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#define IT_MC_PCICR 0x101C
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// Flash/ROM control register offsets from IT8172_BASE
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#define IT_FC_BRCR 0x2000
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#define IT_FC_FCR 0x2004
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#define IT_FC_DCR 0x2008
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// M68K interface bridge configuration header register offset
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#define IT_M68K_MBCSR 0x54
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#define IT_M68K_TMR 0x58
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#define IT_M68K_BCR 0x5C
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#define IT_M68K_BSR 0x5D
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#define IT_M68K_DTR 0x5F
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// Register offset from IT8172_PCI_IO_BASE
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// These registers are accessible through 8172 PCI IO window.
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// INTC
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#define IT_INTC_BASE 0x10000
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#define IT_INTC_LBDNIRR 0x10000
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#define IT_INTC_LBDNIMR 0x10002
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#define IT_INTC_LBDNITR 0x10004
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#define IT_INTC_LBDNIAR 0x10006
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#define IT_INTC_LPCNIRR 0x10010
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#define IT_INTC_LPCNIMR 0x10012
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#define IT_INTC_LPCNITR 0x10014
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#define IT_INTC_LPCNIAR 0x10016
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#define IT_INTC_PDNIRR 0x10020
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#define IT_INTC_PDNIMR 0x10022
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#define IT_INTC_PDNITR 0x10024
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#define IT_INTC_PDNIAR 0x10026
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#define IT_INTC_UMNIRR 0x10030
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#define IT_INTC_UMNITR 0x10034
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#define IT_INTC_UMNIAR 0x10036
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#define IT_INTC_TYPER 0x107FE
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// IT8172 PCI device number
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#define IT_C2P_DEVICE 0
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#define IT_AUDIO_DEVICE 1
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#define IT_DMAC_DEVICE 1
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#define IT_CDMAC_DEVICE 1
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#define IT_USB_DEVICE 1
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#define IT_P2I_DEVICE 1
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#define IT_IDE_DEVICE 1
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#define IT_M68K_DEVICE 1
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// IT8172 PCI function number
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#define IT_C2P_FUNCION 0
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#define IT_AUDIO_FUNCTION 0
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#define IT_DMAC_FUNCTION 1
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#define IT_CDMAC_FUNCTION 2
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#define IT_USB_FUNCTION 3
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#define IT_P2I_FUNCTION 4
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#define IT_IDE_FUNCTION 5
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#define IT_M68K_FUNCTION 6
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// IT8172 GPIO
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#define IT_GPADR 0x13800
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#define IT_GPBDR 0x13808
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#define IT_GPCDR 0x13810
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#define IT_GPACR 0x13802
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#define IT_GPBCR 0x1380A
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#define IT_GPCCR 0x13812
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#define IT_GPAICR 0x13804
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#define IT_GPBICR 0x1380C
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#define IT_GPCICR 0x13814
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#define IT_GPAISR 0x13806
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#define IT_GPBISR 0x1380E
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#define IT_GPCISR 0x13816
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#define IT_GCR 0x13818
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// IT8172 RTC
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#define IT_RTC_BASE 0x14800
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#define IT_RTC_CENTURY 0x14808
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#define IT_RTC_RIR0 0x00
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#define IT_RTC_RTR0 0x01
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#define IT_RTC_RIR1 0x02
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#define IT_RTC_RTR1 0x03
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#define IT_RTC_RIR2 0x04
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#define IT_RTC_RTR2 0x05
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#define IT_RTC_RCTR 0x08
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#define IT_RTC_RA 0x0A
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#define IT_RTC_RB 0x0B
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#define IT_RTC_RC 0x0C
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#define IT_RTC_RD 0x0D
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#define RTC_SEC_INDEX 0x00
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#define RTC_MIN_INDEX 0x02
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#define RTC_HOUR_INDEX 0x04
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#define RTC_DAY_INDEX 0x06
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#define RTC_DATE_INDEX 0x07
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#define RTC_MONTH_INDEX 0x08
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#define RTC_YEAR_INDEX 0x09
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// IT8172 internal device registers
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#define IT_TIMER_BASE 0x10800
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#define IT_CIR0_BASE 0x11000
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#define IT_UART_BASE 0x11800
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#define IT_SCR0_BASE 0x12000
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#define IT_SCR1_BASE 0x12800
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#define IT_PP_BASE 0x13000
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#define IT_I2C_BASE 0x14000
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#define IT_CIR1_BASE 0x15000
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// IT8172 Smart Card Reader offsets from IT_SCR*_BASE
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#define IT_SCR_SFR 0x08
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#define IT_SCR_SCDR 0x09
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// IT8172 IT_SCR_SFR bit definition & mask
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#define IT_SCR_SFR_GATE_UART 0x40
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#define IT_SCR_SFR_GATE_UART_BIT 6
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#define IT_SCR_SFR_GATE_UART_OFF 0
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#define IT_SCR_SFR_GATE_UART_ON 1
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#define IT_SCR_SFR_FET_CHARGE 0x30
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#define IT_SCR_SFR_FET_CHARGE_BIT 4
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#define IT_SCR_SFR_FET_CHARGE_3_3_US 3
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#define IT_SCR_SFR_FET_CHARGE_13_US 2
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#define IT_SCR_SFR_FET_CHARGE_53_US 1
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#define IT_SCR_SFR_FET_CHARGE_213_US 0
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#define IT_SCR_SFR_CARD_FREQ 0x0C
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#define IT_SCR_SFR_CARD_FREQ_BIT 2
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#define IT_SCR_SFR_CARD_FREQ_STOP 3
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#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ 0
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#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ 2
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#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ 1
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#define IT_SCR_SFR_FET_ACTIVE 0x02
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#define IT_SCR_SFR_FET_ACTIVE_BIT 1
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#define IT_SCR_SFR_FET_ACTIVE_INVERT 0
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#define IT_SCR_SFR_FET_ACTIVE_NONINVERT 1
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#define IT_SCR_SFR_ENABLE 0x01
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#define IT_SCR_SFR_ENABLE_BIT 0
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#define IT_SCR_SFR_ENABLE_OFF 0
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#define IT_SCR_SFR_ENABLE_ON 1
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// IT8172 IT_SCR_SCDR bit definition & mask
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#define IT_SCR_SCDR_RESET_MODE 0x80
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#define IT_SCR_SCDR_RESET_MODE_BIT 7
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#define IT_SCR_SCDR_RESET_MODE_ASYNC 0
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#define IT_SCR_SCDR_RESET_MODE_SYNC 1
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#define IT_SCR_SCDR_DIVISOR 0x7F
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#define IT_SCR_SCDR_DIVISOR_BIT 0
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#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1 0x00
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#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2 0x01
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#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3 0x7F
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// IT8172 DMA
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#define IT_DMAC_BASE 0x16000
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#define IT_DMAC_BCAR0 0x00
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#define IT_DMAC_BCAR1 0x04
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#define IT_DMAC_BCAR2 0x08
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#define IT_DMAC_BCAR3 0x0C
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#define IT_DMAC_BCCR0 0x02
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#define IT_DMAC_BCCR1 0x06
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#define IT_DMAC_BCCR2 0x0a
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#define IT_DMAC_BCCR3 0x0e
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#define IT_DMAC_CR 0x10
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#define IT_DMAC_SR 0x12
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#define IT_DMAC_ESR 0x13
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#define IT_DMAC_RQR 0x14
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#define IT_DMAC_MR 0x16
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#define IT_DMAC_EMR 0x17
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#define IT_DMAC_MKR 0x18
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#define IT_DMAC_PAR0 0x20
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#define IT_DMAC_PAR1 0x22
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#define IT_DMAC_PAR2 0x24
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#define IT_DMAC_PAR3 0x26
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// IT8172 IDE
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#define IT_IDE_BASE 0x17800
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#define IT_IDE_STATUS 0x1F7
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// IT8172 Audio Controller
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#define IT_AC_BASE 0x17000
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#define IT_AC_PCMOV 0x00
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#define IT_AC_FMOV 0x02
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#define IT_AC_I2SV 0x04
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#define IT_AC_DRSS 0x06
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#define IT_AC_PCC 0x08
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#define IT_AC_PCDL 0x0A
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#define IT_AC_PCB1STA 0x0C
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#define IT_AC_PCB2STA 0x10
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#define IT_AC_CAPCC 0x14
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#define IT_AC_CAPCDL 0x16
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#define IT_AC_CAPB1STA 0x18
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#define IT_AC_CAPB2STA 0x1C
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#define IT_AC_CODECC 0x22
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#define IT_AC_I2SMC 0x24
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#define IT_AC_VS 0x26
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#define IT_AC_SRCS 0x28
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#define IT_AC_CIRCP 0x2A
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#define IT_AC_CIRDP 0x2C
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#define IT_AC_TM 0x4A
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#define IT_AC_PFDP 0x4C
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#define IT_AC_GC 0x54
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#define IT_AC_IMC 0x56
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#define IT_AC_ISC 0x5B
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#define IT_AC_OPL3SR 0x68
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#define IT_AC_OPL3DWDR 0x69
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#define IT_AC_OPL3AB1W 0x6A
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#define IT_AC_OPL3DW 0x6B
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#define IT_AC_BPDC 0x70
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// IT8172 Timer
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#define IT_TIMER_BASE 0x10800
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#define TIMER_TCVR0 0x00
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#define TIMER_TRVR0 0x02
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#define TIMER_TCR0 0x04
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#define TIMER_TIRR 0x06
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#define TIMER_TCVR1 0x08
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#define TIMER_TRVR1 0x0A
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#define TIMER_TCR1 0x0C
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#define TIMER_TIDR 0x0E
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#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
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#define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
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#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
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#define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
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#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
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#define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
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#endif
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