165 lines
3.5 KiB
C
165 lines
3.5 KiB
C
/*
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* Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
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*
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* Copyright (C) 2002 - 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License v2. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pci.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include "pci-sh4.h"
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/*
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* Direct access to PCI hardware...
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*/
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#define CONFIG_CMD(bus, devfn, where) \
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P1SEGADDR((bus->number << 16) | (devfn << 8) | (where & ~3))
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static DEFINE_SPINLOCK(sh4_pci_lock);
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/*
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* Functions for accessing PCI configuration space with type 1 accesses
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*/
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static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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unsigned long flags;
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u32 data;
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/*
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* PCIPDR may only be accessed as 32 bit words,
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* so we must do byte alignment by hand
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*/
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spin_lock_irqsave(&sh4_pci_lock, flags);
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pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
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data = pci_read_reg(SH4_PCIPDR);
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spin_unlock_irqrestore(&sh4_pci_lock, flags);
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switch (size) {
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case 1:
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*val = (data >> ((where & 3) << 3)) & 0xff;
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break;
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case 2:
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*val = (data >> ((where & 2) << 3)) & 0xffff;
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break;
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case 4:
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*val = data;
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/*
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* Since SH4 only does 32bit access we'll have to do a read,
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* mask,write operation.
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* We'll allow an odd byte offset, though it should be illegal.
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*/
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static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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unsigned long flags;
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int shift;
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u32 data;
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spin_lock_irqsave(&sh4_pci_lock, flags);
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pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
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data = pci_read_reg(SH4_PCIPDR);
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spin_unlock_irqrestore(&sh4_pci_lock, flags);
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switch (size) {
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case 1:
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shift = (where & 3) << 3;
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data &= ~(0xff << shift);
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data |= ((val & 0xff) << shift);
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break;
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case 2:
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shift = (where & 2) << 3;
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data &= ~(0xffff << shift);
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data |= ((val & 0xffff) << shift);
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break;
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case 4:
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data = val;
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break;
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default:
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return PCIBIOS_FUNC_NOT_SUPPORTED;
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}
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pci_write_reg(data, SH4_PCIPDR);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops sh4_pci_ops = {
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.read = sh4_pci_read,
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.write = sh4_pci_write,
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};
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/*
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* Not really related to pci_ops, but it's common and not worth shoving
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* somewhere else for now..
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*/
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static unsigned int pci_probe = PCI_PROBE_CONF1;
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int __init sh4_pci_check_direct(void)
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{
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/*
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* Check if configuration works.
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*/
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if (pci_probe & PCI_PROBE_CONF1) {
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unsigned int tmp = pci_read_reg(SH4_PCIPAR);
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pci_write_reg(P1SEG, SH4_PCIPAR);
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if (pci_read_reg(SH4_PCIPAR) == P1SEG) {
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pci_write_reg(tmp, SH4_PCIPAR);
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printk(KERN_INFO "PCI: Using configuration type 1\n");
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request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1");
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return 0;
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}
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pci_write_reg(tmp, SH4_PCIPAR);
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}
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pr_debug("PCI: pci_check_direct failed\n");
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return -EINVAL;
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}
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/* Handle generic fixups */
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static void __init pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i = 0; i < 4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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char * __init pcibios_setup(char *str)
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{
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if (!strcmp(str, "off")) {
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pci_probe = 0;
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return NULL;
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}
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return str;
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}
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