By merging of uClinux/ARM, we need to treat various CPU cores which have
MMU, MPU or even none for memory management. The memory management
coprocessors are controlled by CP15 register set and the ARM core family
can be categorized by 5 groups by the register ;
G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022,
v6 and the derivations sa1100, sa110, xscale, xsc3.
G-b. CP15 is MPU : 740, 940, 946, 996, 1156.
G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design)
G-d. CP15 is exist, but nothing for memory managemnt : 966, 968.
G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej
This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the
family can be defined as :
- CPU_CP15 only : G-d
- CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable)
- CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable)
- !CPU_CP15 : G-e
Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
fefdaa06cc