196 lines
5.0 KiB
C
196 lines
5.0 KiB
C
/*
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* arch/v850/kernel/sim85e2.c -- Machine-specific stuff for
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* V850E2 RTL simulator
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*
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* Copyright (C) 2002,03 NEC Electronics Corporation
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* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <asm/atomic.h>
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#include <asm/page.h>
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#include <asm/machdep.h>
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#include "mach.h"
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/* There are 4 possible areas we can use:
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IRAM (1MB) is fast for instruction fetches, but slow for data
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DRAM (1020KB) is fast for data, but slow for instructions
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ERAM is cached, so should be fast for both insns and data
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SDRAM is external DRAM, similar to ERAM
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*/
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#define INIT_MEMC_FOR_SDRAM
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#define USE_SDRAM_AREA
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#define KERNEL_IN_SDRAM_AREA
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#define DCACHE_MODE V850E2_CACHE_BTSC_DCM_WT
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/*#define DCACHE_MODE V850E2_CACHE_BTSC_DCM_WB_ALLOC*/
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#ifdef USE_SDRAM_AREA
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#define RAM_START SDRAM_ADDR
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#define RAM_END (SDRAM_ADDR + SDRAM_SIZE)
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#else
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/* When we use DRAM, we need to account for the fact that the end of it is
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used for R0_RAM. */
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#define RAM_START DRAM_ADDR
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#define RAM_END R0_RAM_ADDR
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#endif
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extern void memcons_setup (void);
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#ifdef KERNEL_IN_SDRAM_AREA
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#define EARLY_INIT_SECTION_ATTR __attribute__ ((section (".early.text")))
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#else
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#define EARLY_INIT_SECTION_ATTR __init
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#endif
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void EARLY_INIT_SECTION_ATTR mach_early_init (void)
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{
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/* The sim85e2 simulator tracks `undefined' values, so to make
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debugging easier, we begin by zeroing out all otherwise
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undefined registers. This is not strictly necessary.
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The registers we zero are:
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Every GPR except:
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stack-pointer (r3)
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task-pointer (r16)
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our return addr (r31)
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Every system register (SPR) that we know about except for
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the PSW (SPR 5), which we zero except for the
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disable-interrupts bit.
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*/
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/* GPRs */
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asm volatile (" mov r0, r1 ; mov r0, r2 ");
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asm volatile ("mov r0, r4 ; mov r0, r5 ; mov r0, r6 ; mov r0, r7 ");
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asm volatile ("mov r0, r8 ; mov r0, r9 ; mov r0, r10; mov r0, r11");
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asm volatile ("mov r0, r12; mov r0, r13; mov r0, r14; mov r0, r15");
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asm volatile (" mov r0, r17; mov r0, r18; mov r0, r19");
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asm volatile ("mov r0, r20; mov r0, r21; mov r0, r22; mov r0, r23");
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asm volatile ("mov r0, r24; mov r0, r25; mov r0, r26; mov r0, r27");
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asm volatile ("mov r0, r28; mov r0, r29; mov r0, r30");
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/* SPRs */
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asm volatile ("ldsr r0, 0; ldsr r0, 1; ldsr r0, 2; ldsr r0, 3");
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asm volatile ("ldsr r0, 4");
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asm volatile ("addi 0x20, r0, r1; ldsr r1, 5"); /* PSW */
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asm volatile ("ldsr r0, 16; ldsr r0, 17; ldsr r0, 18; ldsr r0, 19");
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asm volatile ("ldsr r0, 20");
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#ifdef INIT_MEMC_FOR_SDRAM
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/* Settings for SDRAM controller. */
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V850E2_VSWC = 0x0042;
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V850E2_BSC = 0x9286;
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V850E2_BCT(0) = 0xb000; /* was: 0 */
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V850E2_BCT(1) = 0x000b;
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V850E2_ASC = 0;
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V850E2_LBS = 0xa9aa; /* was: 0xaaaa */
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V850E2_LBC(0) = 0;
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V850E2_LBC(1) = 0; /* was: 0x3 */
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V850E2_BCC = 0;
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V850E2_RFS(4) = 0x800a; /* was: 0xf109 */
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V850E2_SCR(4) = 0x2091; /* was: 0x20a1 */
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V850E2_RFS(3) = 0x800c;
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V850E2_SCR(3) = 0x20a1;
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V850E2_DWC(0) = 0;
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V850E2_DWC(1) = 0;
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#endif
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#if 0
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#ifdef CONFIG_V850E2_SIM85E2S
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/* Turn on the caches. */
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V850E2_CACHE_BTSC = V850E2_CACHE_BTSC_ICM | DCACHE_MODE;
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V850E2_BHC = 0x1010;
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#elif CONFIG_V850E2_SIM85E2C
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V850E2_CACHE_BTSC |= (V850E2_CACHE_BTSC_ICM | V850E2_CACHE_BTSC_DCM0);
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V850E2_BUSM_BHC = 0xFFFF;
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#endif
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#else
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V850E2_BHC = 0;
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#endif
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/* Don't stop the simulator at `halt' instructions. */
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SIM85E2_NOTHAL = 1;
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/* Ensure that the simulator halts on a panic, instead of going
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into an infinite loop inside the panic function. */
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panic_timeout = -1;
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}
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void __init mach_setup (char **cmdline)
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{
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memcons_setup ();
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}
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void mach_get_physical_ram (unsigned long *ram_start, unsigned long *ram_len)
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{
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*ram_start = RAM_START;
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*ram_len = RAM_END - RAM_START;
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}
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void __init mach_sched_init (struct irqaction *timer_action)
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{
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/* The simulator actually cycles through all interrupts
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periodically. We just pay attention to IRQ0, which gives us
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1/64 the rate of the periodic interrupts. */
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setup_irq (0, timer_action);
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}
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void mach_gettimeofday (struct timespec *tv)
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{
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tv->tv_sec = 0;
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tv->tv_nsec = 0;
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}
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/* Interrupts */
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struct v850e_intc_irq_init irq_inits[] = {
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{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
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{ 0 }
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};
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struct hw_interrupt_type hw_itypes[1];
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/* Initialize interrupts. */
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void __init mach_init_irqs (void)
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{
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v850e_intc_init_irq_types (irq_inits, hw_itypes);
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}
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void machine_halt (void) __attribute__ ((noreturn));
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void machine_halt (void)
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{
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SIM85E2_SIMFIN = 0; /* Halt immediately. */
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for (;;) {}
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}
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void machine_restart (char *__unused)
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{
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machine_halt ();
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}
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void machine_power_off (void)
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{
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machine_halt ();
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}
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