[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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/*
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2008-03-28 02:51:41 +08:00
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* include/asm-arm/arch-orion5x/io.h
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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2008-03-28 02:51:41 +08:00
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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* warranty of any kind, whether express or implied.
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*/
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2008-03-28 02:51:41 +08:00
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#ifndef __ASM_ARCH_IO_H
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#define __ASM_ARCH_IO_H
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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2008-03-28 02:51:41 +08:00
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#include "orion5x.h"
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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#define IO_SPACE_LIMIT 0xffffffff
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2008-03-28 02:51:41 +08:00
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static inline void __iomem *
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__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
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{
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void __iomem *retval;
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2008-04-26 02:28:55 +08:00
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unsigned long offs = paddr - ORION5X_REGS_PHYS_BASE;
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if (mtype == MT_DEVICE && size && offs < ORION5X_REGS_SIZE &&
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size <= ORION5X_REGS_SIZE && offs + size <= ORION5X_REGS_SIZE) {
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retval = (void __iomem *)ORION5X_REGS_VIRT_BASE + offs;
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2008-03-28 02:51:41 +08:00
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} else {
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retval = __arm_ioremap(paddr, size, mtype);
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}
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return retval;
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}
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static inline void
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__arch_iounmap(void __iomem *addr)
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{
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2008-03-28 02:51:41 +08:00
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if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
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addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
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2008-03-28 02:51:41 +08:00
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__iounmap(addr);
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}
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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static inline void __iomem *__io(unsigned long addr)
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{
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return (void __iomem *)addr;
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}
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2008-03-28 02:51:41 +08:00
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#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
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#define __arch_iounmap(a) __arch_iounmap(a)
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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#define __io(a) __io(a)
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#define __mem_pci(a) (a)
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2008-03-28 02:51:41 +08:00
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/*****************************************************************************
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* Helpers to access Orion registers
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****************************************************************************/
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/*
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* These are not preempt-safe. Locks, if needed, must be taken
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* care of by the caller.
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*/
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2008-05-28 22:43:48 +08:00
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#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
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#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
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2008-03-28 02:51:41 +08:00
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[ARM] basic support for the Marvell Orion SoC family
The Marvell Orion is a family of ARM SoCs with a DDR/DDR2 memory
controller, 10/100/1000 ethernet MAC, and USB 2.0 interfaces,
and, depending on the specific model, PCI-E interface, PCI-X
interface, SATA controllers, crypto unit, SPI interface, SDIO
interface, device bus, NAND controller, DMA engine and/or XOR
engine.
This contains the basic structure and architecture register definitions.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Reviewed-by: Nicolas Pitre <nico@marvell.com>
Reviewed-by: Lennert Buytenhek <buytenh@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-10-24 03:14:41 +08:00
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#endif
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