176 lines
5.2 KiB
C
176 lines
5.2 KiB
C
/*
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* Blackfin CPLB initialization
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*
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#include <asm/mem_map.h>
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struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
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struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS] PDT_ATTR;
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int first_switched_icplb PDT_ATTR;
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int first_switched_dcplb PDT_ATTR;
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struct cplb_boundary dcplb_bounds[9] PDT_ATTR;
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struct cplb_boundary icplb_bounds[7] PDT_ATTR;
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int icplb_nr_bounds PDT_ATTR;
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int dcplb_nr_bounds PDT_ATTR;
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void __init generate_cplb_tables_cpu(unsigned int cpu)
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{
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int i_d, i_i;
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unsigned long addr;
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struct cplb_entry *d_tbl = dcplb_tbl[cpu];
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struct cplb_entry *i_tbl = icplb_tbl[cpu];
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printk(KERN_INFO "NOMPU: setting up cplb tables\n");
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i_d = i_i = 0;
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#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
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/* Set up the zero page. */
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d_tbl[i_d].addr = 0;
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d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
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i_tbl[i_i].addr = 0;
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i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
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#endif
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/* Cover kernel memory with 4M pages. */
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addr = 0;
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for (; addr < memory_start; addr += 4 * 1024 * 1024) {
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d_tbl[i_d].addr = addr;
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d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
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i_tbl[i_i].addr = addr;
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i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
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}
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/* Cover L1 memory. One 4M area for code and data each is enough. */
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if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
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d_tbl[i_d].addr = L1_DATA_A_START;
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d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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}
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i_tbl[i_i].addr = L1_CODE_START;
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i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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first_switched_dcplb = i_d;
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first_switched_icplb = i_i;
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BUG_ON(first_switched_dcplb > MAX_CPLBS);
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BUG_ON(first_switched_icplb > MAX_CPLBS);
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while (i_d < MAX_CPLBS)
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d_tbl[i_d++].data = 0;
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while (i_i < MAX_CPLBS)
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i_tbl[i_i++].data = 0;
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}
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void __init generate_cplb_tables_all(void)
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{
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int i_d, i_i;
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i_d = 0;
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/* Normal RAM, including MTD FS. */
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#ifdef CONFIG_MTD_UCLINUX
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dcplb_bounds[i_d].eaddr = memory_mtd_start + mtd_size;
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#else
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dcplb_bounds[i_d].eaddr = memory_end;
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#endif
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dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
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/* DMA uncached region. */
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if (DMA_UNCACHED_REGION) {
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dcplb_bounds[i_d].eaddr = _ramend;
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dcplb_bounds[i_d++].data = SDRAM_DNON_CHBL;
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}
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if (_ramend != physical_mem_end) {
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/* Reserved memory. */
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dcplb_bounds[i_d].eaddr = physical_mem_end;
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dcplb_bounds[i_d++].data = (reserved_mem_dcache_on ?
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SDRAM_DGENERIC : SDRAM_DNON_CHBL);
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}
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/* Addressing hole up to the async bank. */
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dcplb_bounds[i_d].eaddr = ASYNC_BANK0_BASE;
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dcplb_bounds[i_d++].data = 0;
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/* ASYNC banks. */
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dcplb_bounds[i_d].eaddr = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE;
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dcplb_bounds[i_d++].data = SDRAM_EBIU;
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/* Addressing hole up to BootROM. */
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dcplb_bounds[i_d].eaddr = BOOT_ROM_START;
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dcplb_bounds[i_d++].data = 0;
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/* BootROM -- largest one should be less than 1 meg. */
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dcplb_bounds[i_d].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
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dcplb_bounds[i_d++].data = SDRAM_DGENERIC;
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if (L2_LENGTH) {
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/* Addressing hole up to L2 SRAM. */
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dcplb_bounds[i_d].eaddr = L2_START;
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dcplb_bounds[i_d++].data = 0;
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/* L2 SRAM. */
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dcplb_bounds[i_d].eaddr = L2_START + L2_LENGTH;
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dcplb_bounds[i_d++].data = L2_DMEMORY;
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}
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dcplb_nr_bounds = i_d;
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BUG_ON(dcplb_nr_bounds > ARRAY_SIZE(dcplb_bounds));
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i_i = 0;
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/* Normal RAM, including MTD FS. */
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#ifdef CONFIG_MTD_UCLINUX
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icplb_bounds[i_i].eaddr = memory_mtd_start + mtd_size;
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#else
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icplb_bounds[i_i].eaddr = memory_end;
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#endif
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icplb_bounds[i_i++].data = SDRAM_IGENERIC;
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/* DMA uncached region. */
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if (DMA_UNCACHED_REGION) {
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icplb_bounds[i_i].eaddr = _ramend;
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icplb_bounds[i_i++].data = 0;
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}
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if (_ramend != physical_mem_end) {
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/* Reserved memory. */
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icplb_bounds[i_i].eaddr = physical_mem_end;
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icplb_bounds[i_i++].data = (reserved_mem_icache_on ?
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SDRAM_IGENERIC : SDRAM_INON_CHBL);
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}
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/* Addressing hole up to BootROM. */
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icplb_bounds[i_i].eaddr = BOOT_ROM_START;
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icplb_bounds[i_i++].data = 0;
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/* BootROM -- largest one should be less than 1 meg. */
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icplb_bounds[i_i].eaddr = BOOT_ROM_START + (1 * 1024 * 1024);
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icplb_bounds[i_i++].data = SDRAM_IGENERIC;
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if (L2_LENGTH) {
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/* Addressing hole up to L2 SRAM, including the async bank. */
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icplb_bounds[i_i].eaddr = L2_START;
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icplb_bounds[i_i++].data = 0;
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/* L2 SRAM. */
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icplb_bounds[i_i].eaddr = L2_START + L2_LENGTH;
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icplb_bounds[i_i++].data = L2_IMEMORY;
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}
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icplb_nr_bounds = i_i;
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BUG_ON(icplb_nr_bounds > ARRAY_SIZE(icplb_bounds));
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}
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